arm: add CONFIG_MACH_TYPE setting and documentation

[oweals/u-boot.git] / README

diff --git a/README b/README
index 7ee16323d1c0c814085f1569058d52705b60c202..7b27c992e3d821067596770f8b40ddcaa9d97f5c 100644 (file)
--- a/README
+++ b/README
@@ -442,6 +442,16 @@ The following options need to be configured:
                crash. This is needed for buggy hardware (uc101) where
                no pull down resistor is connected to the signal IDE5V_DD7.
 
+               CONFIG_MACH_TYPE        [relevant for ARM only][mandatory]
+
+               This setting is mandatory for all boards that have only one
+               machine type and must be used to specify the machine type
+               number as it appears in the ARM machine registry
+               (see http://www.arm.linux.org.uk/developer/machines/).
+               Only boards that have multiple machine types supported
+               in a single configuration file and the machine type is
+               runtime discoverable, do not have to use this setting.
+
 - vxWorks boot parameters:
 
                bootvx constructs a valid bootline using the following
@@ -465,6 +475,12 @@ The following options need to be configured:
                CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
                CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
 
+- Cache Configuration for ARM:
+               CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
+                                     controller
+               CONFIG_SYS_PL310_BASE - Physical base address of PL310
+                                       controller register space
+
 - Serial Ports:
                CONFIG_PL010_SERIAL
 
@@ -2942,6 +2958,12 @@ Low Level (hardware related) configuration options:
                one, specify here. Note that the value must resolve
                to something your driver can deal with.
 
+- CONFIG_SYS_DDR_RAW_TIMING
+               Get DDR timing information from other than SPD. Common with
+               soldered DDR chips onboard without SPD. DDR raw timing
+               parameters are extracted from datasheet and hard-coded into
+               header files or board specific files.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.