checkpatch: fix left brace warning

[oweals/u-boot.git] / README

diff --git a/README b/README
index b5f6471670c3b256d583b00a0877f70a12976b11..43f307f30fd8ce3b1fd5a0ee098399e7ff2bb2f4 100644 (file)
--- a/README
+++ b/README
@@ -611,6 +611,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
                Number of controllers used for other than main memory.
 
+               CONFIG_SYS_FSL_HAS_DP_DDR
+               Defines the SoC has DP-DDR used for DPAA.
+
                CONFIG_SYS_FSL_SEC_BE
                Defines the SEC controller register space as Big Endian
 
@@ -3866,7 +3869,15 @@ Configuration Settings:
                Scratch address used by the alternate memory test
                You only need to set this if address zero isn't writeable
 
-- CONFIG_SYS_MEM_TOP_HIDE (PPC only):
+- CONFIG_SYS_MEM_RESERVE_SECURE
+               If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+               is substracted from total RAM and won't be reported to OS.
+               This memory can be used as secure memory. A variable
+               gd->secure_ram is used to track the location. In systems
+               the RAM base is not zero, or RAM is divided into banks,
+               this variable needs to be recalcuated to get the address.
+
+- CONFIG_SYS_MEM_TOP_HIDE:
                If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
                this specified memory area will get subtracted from the top
                (end) of RAM and won't get "touched" at all by U-Boot. By
@@ -5045,8 +5056,8 @@ This firmware often needs to be loaded during U-Boot booting.
 - CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
        Define minimum DDR size required for debug server image
 
-- CONFIG_SYS_MEM_TOP_HIDE_MIN
-       Define minimum DDR size to be hided from top of the DDR memory
+- CONFIG_SYS_MC_RSV_MEM_ALIGN
+       Define alignment of reserved memory MC requires
 
 Reproducible builds
 -------------------