board/bsc9131rdb: Add DSP side tlb and laws

[oweals/u-boot.git] / README

diff --git a/README b/README
index c3d6ca5d2d2439e4572959b701e477c6bec00eec..2dd0bc063408f1d0aae3ed1450165d783deb845b 100644 (file)
--- a/README
+++ b/README
@@ -422,6 +422,13 @@ The following options need to be configured:
                This is the value to write into CCSR offset 0x18600
                according to the A004510 workaround.
 
+               CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+               This value denotes start offset of M2 memory
+               which is directly connected to the DSP core.
+
+               CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+               This value denotes start offset of DSP CCSR space.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN