Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx

[oweals/u-boot.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index ac3be077d14a6c39a3aff439695ecd6bad1e7abb..d47dda22f7942ba2313ec13e879d7ff122f2991f 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,7 +1,46 @@
+======================================================================
+Changes since U-Boot 1.1.4:
+======================================================================
+
+* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
+  Patch by Kumar Gala, 25 Jan 2006
+
+* Fixed defines for MPC83xx SICRL register to match current specs
+  Patch by Kumar Gala, 23 Jan 2006
+
+* Only disable the MPC83xx watchdog if its enabled out of reset.
+  If its disabled out of reset SW can later enable it if so desired
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Allow config of GPIO direction & data registers at boot on 83xx
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Enable time handling on 83xx
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Make System IO Config Registers board configurable on MPC83xx
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for 28F256J3A flah (=> 64 MB) on PM520 board
+
+* Fix compiler problem with at91rm9200dk board.
+  Patch by Eugen Bigz, 19 Dec 2005
+
 ======================================================================
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
+  - Changed GPIO setup to enable another address line in order to
+    address 64M of FLASH.
+  - Added function sdram_tr1_set to auto calculate the tr1 value for
+    the DDR.
+  Patch by Steven Blakeslee, 12 Dec 2005
+
+* MPC5200:  Set PCI retry counter to 0 = infinite retry;
+  The default of 255 is too short for slow devices.
+  Patch by Martin Nykodym, 12 Dec 2005
+
 * Change port configuration for O2DNT (CODEC1 on PSC1).
 
 * Fix register for PCI async mode on PPC440EP