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ramips: fix image validation errors
[oweals/openwrt.git]
/
target
/
linux
/
ar71xx
/
patches-4.4
/
620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
diff --git
a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 6fd6dafd47740953782bb0db0f694fd54abea47c..777f7b2c8838f2c93f79d5d5212f90b2bd82ced3 100644
(file)
--- a/
target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/
target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@
-22,7
+22,7
@@
meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -11
7,6 +117
,10 @@ config SOC_AR934X
+@@ -11
6,6 +116
,10 @@ config SOC_AR934X
select PCI_AR724X if PCI
def_bool n
select PCI_AR724X if PCI
def_bool n
@@
-33,7
+33,7
@@
meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
config SOC_QCA955X
select HW_HAS_PCI
select PCI_AR724X if PCI
config SOC_QCA955X
select HW_HAS_PCI
select PCI_AR724X if PCI
-@@ -15
6,7 +160
,7 @@ config ATH79_DEV_USB
+@@ -15
5,7 +159
,7 @@ config ATH79_DEV_USB
def_bool n
config ATH79_DEV_WMAC
def_bool n
config ATH79_DEV_WMAC
@@
-147,7
+147,7
@@
meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
else
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
else
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
-@@ -10
4,6 +104
,8 @@ void ath79_device_reset_set(u32 mask)
+@@ -10
3,6 +103
,8 @@ void ath79_device_reset_set(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
@@
-156,7
+156,7
@@
meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
else
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
else
-@@ -13
2,6 +134
,8 @@ void ath79_device_reset_clear(u32 mask)
+@@ -13
1,6 +133
,8 @@ void ath79_device_reset_clear(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
@@
-335,10
+335,10
@@
meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
+
+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
+
+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
-+ ath79_ddr_wb_flush(
QCA953X_DDR_REG_FLUSH_PCIE
);
++ ath79_ddr_wb_flush(
3
);
+ generic_handle_irq(ATH79_IP2_IRQ(0));
+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
+ generic_handle_irq(ATH79_IP2_IRQ(0));
+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
-+ ath79_ddr_wb_flush(
QCA953X_DDR_REG_FLUSH_WMAC
);
++ ath79_ddr_wb_flush(
4
);
+ generic_handle_irq(ATH79_IP2_IRQ(1));
+ } else {
+ spurious_interrupt();
+ generic_handle_irq(ATH79_IP2_IRQ(1));
+ } else {
+ spurious_interrupt();