asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
WATCHDOG_RESET();
}
/* wait for all dcbst to complete on bus */
asm volatile("sync" : : : "memory");
asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
WATCHDOG_RESET();
}
/* wait for all dcbst to complete on bus */
asm volatile("sync" : : : "memory");