-#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z020" }
-
-#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z030" }
-
-#define XILINX_XC7Z035_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z035" }
-
-#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z045" }
-
-#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
- "7z100" }
+#if defined(CONFIG_FPGA)
+#define ZYNQ_DESC(name) { \
+ .idcode = XILINX_ZYNQ_XC##name, \
+ .fpga_size = XILINX_XC##name##_SIZE, \
+ .devicename = XILINX_XC##name##_NAME \
+ }
+#else
+#define ZYNQ_DESC(name) { \
+ .idcode = XILINX_ZYNQ_XC##name, \
+ .devicename = XILINX_XC##name##_NAME \
+ }
+#endif