-#define SDR0_UARTX_UXICS_MASK 0xF0000000
-#define SDR0_UARTX_UXICS_PLB 0x20000000
-#define SDR0_UARTX_UXEC_MASK 0x00800000
-#define SDR0_UARTX_UXEC_INT 0x00000000
-#define SDR0_UARTX_UXEC_EXT 0x00800000
-#define SDR0_UARTX_UXDIV_MASK 0x000000FF
-#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
-#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
-
-#define SDR0_CP440 0x0180
-#define SDR0_CP440_ERPN_MASK 0x30000000
-#define SDR0_CP440_ERPN_MASK_HI 0x3000
-#define SDR0_CP440_ERPN_MASK_LO 0x0000
-#define SDR0_CP440_ERPN_EBC 0x10000000
-#define SDR0_CP440_ERPN_EBC_HI 0x1000
-#define SDR0_CP440_ERPN_EBC_LO 0x0000
-#define SDR0_CP440_ERPN_PCI 0x20000000
-#define SDR0_CP440_ERPN_PCI_HI 0x2000
-#define SDR0_CP440_ERPN_PCI_LO 0x0000
-#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
-#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
-#define SDR0_CP440_NTO1_MASK 0x00000002
-#define SDR0_CP440_NTO1_NTOP 0x00000000
-#define SDR0_CP440_NTO1_NTO1 0x00000002
-#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
-#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
-
-#define SDR0_XCR0 0x01C0
-#define SDR0_XCR1 0x01C3
-#define SDR0_XCR2 0x01C6
-#define SDR0_XCRn_PAE_MASK 0x80000000
-#define SDR0_XCRn_PAE_DISABLE 0x00000000
-#define SDR0_XCRn_PAE_ENABLE 0x80000000
-#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
-#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
-#define SDR0_XCRn_PHCE_MASK 0x40000000
-#define SDR0_XCRn_PHCE_DISABLE 0x00000000
-#define SDR0_XCRn_PHCE_ENABLE 0x40000000
-#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
-#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
-#define SDR0_XCRn_PISE_MASK 0x20000000
-#define SDR0_XCRn_PISE_DISABLE 0x00000000
-#define SDR0_XCRn_PISE_ENABLE 0x20000000
-#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
-#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
-#define SDR0_XCRn_PCWE_MASK 0x10000000
-#define SDR0_XCRn_PCWE_DISABLE 0x00000000
-#define SDR0_XCRn_PCWE_ENABLE 0x10000000
-#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
-#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
-#define SDR0_XCRn_PPIM_MASK 0x0F000000
-#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
-#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
-#define SDR0_XCRn_PR64E_MASK 0x00800000
-#define SDR0_XCRn_PR64E_DISABLE 0x00000000
-#define SDR0_XCRn_PR64E_ENABLE 0x00800000
-#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
-#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
-#define SDR0_XCRn_PXFS_MASK 0x00600000
-#define SDR0_XCRn_PXFS_100_133 0x00000000
-#define SDR0_XCRn_PXFS_66_100 0x00200000
-#define SDR0_XCRn_PXFS_50_66 0x00400000
-#define SDR0_XCRn_PXFS_0_33 0x00600000
-#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
-#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
-
-#define SDR0_XPLLC0 0x01C1
-#define SDR0_XPLLD0 0x01C2
-#define SDR0_XPLLC1 0x01C4
-#define SDR0_XPLLD1 0x01C5
-#define SDR0_XPLLC2 0x01C7
-#define SDR0_XPLLD2 0x01C8
-#define SDR0_SRST 0x0200