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board: ti: DRA7: Add DP83867 TI phy for rev c
[oweals/u-boot.git]
/
include
/
configs
/
tao3530.h
diff --git
a/include/configs/tao3530.h
b/include/configs/tao3530.h
index 7d2c0d2fa75c2e87b49a2d2bb4d6bd6f15e4a95f..73cd0a028b67ecd3f333785307c4900097252ef8 100644
(file)
--- a/
include/configs/tao3530.h
+++ b/
include/configs/tao3530.h
@@
-13,6
+13,8
@@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* High Level Configuration Options
*/
/*
* High Level Configuration Options
*/
@@
-20,14
+22,17
@@
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_OMAP3_TAO3530 2836
#define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define MACH_TYPE_OMAP3_TAO3530 2836
#define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap
3
.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
/*
* Display CPU and Board information
@@
-41,8
+46,6
@@
#define CONFIG_MISC_INIT_R
#define CONFIG_MISC_INIT_R
-#define CONFIG_OF_LIBFDT
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@
-63,7
+66,6
@@
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
@@
-90,8
+92,6
@@
#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
/* commands to include */
#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
@@
-108,11
+108,6
@@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_OMAP34XX
@@
-129,7
+124,6
@@
/*
* Board NAND Info.
*/
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
@@
-139,7
+133,7
@@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
/* Environment information */
#define CONFIG_BOOTDELAY 3
/* Environment information */
#define CONFIG_BOOTDELAY 3
@@
-199,7
+193,6
@@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "TAO-3530 # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* turn on command-line edit/hist/auto */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* turn on command-line edit/hist/auto */
@@
-346,7
+339,6
@@
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the