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mx53evk: Fix CONFIG_SYS_MEMTEST_END
[oweals/u-boot.git]
/
include
/
configs
/
pm9263.h
diff --git
a/include/configs/pm9263.h
b/include/configs/pm9263.h
index 0af1280370b3a9f27831abc0a266e3c62d379102..bf31c13bdcfdbcc4e71625c97d6c90e2ca02983c 100644
(file)
--- a/
include/configs/pm9263.h
+++ b/
include/configs/pm9263.h
@@
-1,6
+1,6
@@
/*
* (C) Copyright 2007-2008
/*
* (C) Copyright 2007-2008
- * Stelian Pop <stelian
.pop@leadtechdesign.com
>
+ * Stelian Pop <stelian
@popies.net
>
* Lead Tech Design <www.leadtechdesign.com>
* Ilko Iliev <www.ronetix.at>
*
* Lead Tech Design <www.leadtechdesign.com>
* Ilko Iliev <www.ronetix.at>
*
@@
-28,6
+28,12
@@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef __CONFIG_H
#define __CONFIG_H
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
/* ARM asynchronous clock */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* ARM asynchronous clock */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@
-35,53
+41,53
@@
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */
-#define AT91_MAIN_CLOCK 18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ 1000
-#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
-#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_SYS_TEXT_BASE 0
+
+#define MACH_TYPE_PM9263 1475
+#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
/* clocks */
#define CONFIG_SYS_MOR_VAL \
/* clocks */
#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MO
SCEN |
\
+ (AT91_PMC_MO
R_MOSCEN |
\
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA
_WR_ERRATA
| /* Bit 29 must be 1 when prog */ \
- AT91_PMC_
OUT |
\
- AT91_PMC_PLL
COUNT | /* PLL Counter */
\
+ (AT91_PMC_PLLA
R_29
| /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_
PLLXR_OUT(3) |
\
+ AT91_PMC_PLL
XR_PLLCOUNT(0x3f) | /* PLL Counter */
\
(2 << 28) | /* PLL Clock Frequency Range */ \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(2 << 28) | /* PLL Clock Frequency Range */ \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
+ (AT91_PMC_MCKR_CSS_SLOW | \
+ AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
+ (AT91_PMC_MCKR_CSS_PLLA | \
+ AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_2)
#else
/* PCK/4 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
#else
/* PCK/4 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91RM9200_PMC_MDIV_3 | \
- AT91_PMC_PDIV_1)
+ (AT91_PMC_MCKR_CSS_SLOW | \
+ AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_4)
/* PCK/4 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
/* PCK/4 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91RM9200_PMC_MDIV_3 | \
- AT91_PMC_PDIV_1)
+ (AT91_PMC_MCKR_CSS_PLLA | \
+ AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_4)
#endif
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
#endif
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
@@
-89,8
+95,8
@@
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_
EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
\
- AT91_MATRIX_
EBI0_CS1A_SDRAMC
)
+ (AT91_MATRIX_
CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |
\
+ AT91_MATRIX_
CSA_EBI_CS1A
)
/* SDRAM */
/* SDRAMC_MR Mode register */
/* SDRAM */
/* SDRAMC_MR Mode register */
@@
-133,49
+139,48
@@
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_
NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_
(10) | \
- AT91_SMC_
NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_
(10))
+ (AT91_SMC_
SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR
(10) | \
+ AT91_SMC_
SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD
(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_
NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_
(11) | \
- AT91_SMC_
NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_
(11))
+ (AT91_SMC_
PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR
(11) | \
+ AT91_SMC_
PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD
(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_
NWECYCLE_(22) | AT91_SMC_NRDCYCLE_
(22))
+ (AT91_SMC_
CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD
(22))
#define CONFIG_SYS_SMC0_MODE0_VAL \
#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_
READMODE | AT91_SMC_WRITEMODE |
\
- AT91_SMC_
DBW_16 |
\
- AT91_SMC_
TDFMODE |
\
- AT91_SMC_
TDF_
(6))
+ (AT91_SMC_
MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
\
+ AT91_SMC_
MODE_DBW_16 |
\
+ AT91_SMC_
MODE_TDF |
\
+ AT91_SMC_
MODE_TDF_CYCLE
(6))
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
- AT91_RSTC_
PROCRST |
\
- AT91_RSTC_
RSTTYP_WAKEUP |
\
- AT91_RSTC_
RSTTYP_WATCHDOG
)
+ AT91_RSTC_
CR_PROCRST |
\
+ AT91_RSTC_
MR_ERSTL(1) |
\
+ AT91_RSTC_
MR_ERSTL(2)
)
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_
WDIDLEHLT | AT91_WDT_WDDBGHLT |
\
- AT91_WDT_
WDV |
\
- AT91_WDT_
WDDIS |
\
- AT91_WDT_
WDD
)
+ (AT91_WDT_
MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |
\
+ AT91_WDT_
MR_WDV(0xfff) |
\
+ AT91_WDT_
MR_WDDIS |
\
+ AT91_WDT_
MR_WDD(0xfff)
)
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_USER_LOWLEVEL_INIT 1
#define CONFIG_USER_LOWLEVEL_INIT 1
+#define CONFIG_BOARD_EARLY_INIT_F
/*
* Hardware drivers
*/
/*
* Hardware drivers
*/
+#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#define CONFIG_ATMEL_USART 1
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-#undef CONFIG_USART2
-#define CONFIG_USART3 1 /* USART 3 is DBGU */
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_SYS
/* LCD */
#define CONFIG_LCD 1
/* LCD */
#define CONFIG_LCD 1
@@
-193,8
+198,8
@@
/* LED */
#define CONFIG_AT91_LED
/* LED */
#define CONFIG_AT91_LED
-#define CONFIG_RED_LED AT91_PI
N_PB7
/* this is the power led */
-#define CONFIG_GREEN_LED AT91_PI
N_PB8
/* this is the user1 led */
+#define CONFIG_RED_LED AT91_PI
O_PORTB, 7
/* this is the power led */
+#define CONFIG_GREEN_LED AT91_PI
O_PORTB, 8
/* this is the user1 led */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 3
@@
-212,11
+217,11
@@
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
@@
-248,7
+253,6
@@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
@@
-256,8
+260,8
@@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PI
N_PD
15
-#define CONFIG_SYS_NAND_READY_PIN AT91_PI
N_PB
30
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PI
O_PORTD,
15
+#define CONFIG_SYS_NAND_READY_PIN AT91_PI
O_PORTB,
30
#endif
#endif
@@
-271,11
+275,15
@@
/* PSRAM */
#define PHYS_PSRAM 0x70000000
#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
/* PSRAM */
#define PHYS_PSRAM 0x70000000
#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
+/* Slave EBI1, PSRAM connected */
+#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
+ AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
+ AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
+ AT91_MATRIX_SCFG_SLOT_CYCLE(255))
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_RMII 1
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_RMII 1
-#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R 1
@@
-347,7
+355,7
@@
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
#define CONFIG_BOOTCOMMAND "run flashboot"
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
#define CONFIG_BOOTCOMMAND "run flashboot"
-#define CONFIG_ROOTPATH
/ronetix/rootfs
+#define CONFIG_ROOTPATH
"/ronetix/rootfs"
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
#define CONFIG_CON_ROT "fbcon=rotate:3 "
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
#define CONFIG_CON_ROT "fbcon=rotate:3 "
@@
-400,7
+408,10
@@
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */