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mx6qsabrelite: add and enable USB Host 1 support
[oweals/u-boot.git]
/
include
/
configs
/
omap3_sdp3430.h
diff --git
a/include/configs/omap3_sdp3430.h
b/include/configs/omap3_sdp3430.h
index a47cb6bbc44758effa2688aa145a4b1d68fe4407..404aed2f5f9cbe7a1becc1ff7b97ae3be34ab2c6 100644
(file)
--- a/
include/configs/omap3_sdp3430.h
+++ b/
include/configs/omap3_sdp3430.h
@@
-38,7
+38,6
@@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#define CONFIG_SDRC /* The chip has SDRC controller */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@
-138,9
+137,6
@@
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
-/* DDR - I use Infineon DDR */
-#define CONFIG_OMAP3_INFINEON_DDR 1
-
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
@@
-189,8
+185,9
@@
*/
#if defined(CONFIG_CMD_MMC)
*/
#if defined(CONFIG_CMD_MMC)
+#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_MMC 1
-#define CONFIG_OMAP
3_MMC
1
+#define CONFIG_OMAP
_HSMMC
1
#define CONFIG_DOS_PARTITION 1
#endif
#define CONFIG_DOS_PARTITION 1
#endif
@@
-200,7
+197,6
@@
*/
#if defined(CONFIG_CMD_NET)
*/
#if defined(CONFIG_CMD_NET)
-#define CONFIG_NET_MULTI
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE DEBUG_BASE
#define CONFIG_LAN91C96_EXT_PHY
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE DEBUG_BASE
#define CONFIG_LAN91C96_EXT_PHY
@@
-304,10
+300,6
@@
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
@@
-323,9
+315,6
@@
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C 1
-
/*--------------------------------------------------------------------------*/
/*
/*--------------------------------------------------------------------------*/
/*
@@
-358,4
+347,6
@@
* - rest for filesystem
*/
* - rest for filesystem
*/
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */
#endif /* __CONFIG_H */