- */
-#define CONFIG_NR_DRAM_BANKS 4
-#define PHYS_SDRAM_1 0x00000000
-#define PHYS_SDRAM_SIZE_1 0x00800000
-#define PHYS_SDRAM_2 0x01000000
-#define PHYS_SDRAM_SIZE_2 0x00800000
-#define PHYS_SDRAM_3 0x04000000
-#define PHYS_SDRAM_SIZE_3 0x00800000
-#define PHYS_SDRAM_4 0x05000000
-#define PHYS_SDRAM_SIZE_4 0x00800000
-#define CONFIG_EDB93XX_SDCS3
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x007fffff
-
-#elif defined(CONFIG_EDB9302A)
-/*
- * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
- * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
- * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
- */
-#define CONFIG_NR_DRAM_BANKS 4
-#define PHYS_SDRAM_1 0xc0000000
-#define PHYS_SDRAM_SIZE_1 0x00800000
-#define PHYS_SDRAM_2 0xc1000000
-#define PHYS_SDRAM_SIZE_2 0x00800000
-#define PHYS_SDRAM_3 0xc4000000
-#define PHYS_SDRAM_SIZE_3 0x00800000
-#define PHYS_SDRAM_4 0xc5000000
-#define PHYS_SDRAM_SIZE_4 0x00800000
-#define CONFIG_EDB93XX_SDCS0
-#define CONFIG_SYS_MEMTEST_START 0xc0100000
-#define CONFIG_SYS_MEMTEST_END 0xc07fffff
-
-#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
- defined(CONFIG_EDB9315)
-/*