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8xxx: Second UART port added for MPC85xx, MPC83xx, MPC86xx processors
[oweals/u-boot.git]
/
include
/
configs
/
delta.h
diff --git
a/include/configs/delta.h
b/include/configs/delta.h
index 08b28ca8ac7f3e5809924495c356d76c527ba676..e7186e83990a59bd5e86f279bc84afb3c0c5cbf5 100644
(file)
--- a/
include/configs/delta.h
+++ b/
include/configs/delta.h
@@
-34,12
+34,14
@@
#ifdef CONFIG_LCD
#define CONFIG_SHARP_LM8V31
#endif
#ifdef CONFIG_LCD
#define CONFIG_SHARP_LM8V31
#endif
-/* #define CONFIG_MMC 1 */
#define BOARD_LATE_INIT 1
#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define BOARD_LATE_INIT 1
#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+
/*
* Size of malloc() pool
*/
/*
* Size of malloc() pool
*/
@@
-80,6
+82,7
@@
/*
* select serial console configuration
*/
/*
* select serial console configuration
*/
+#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_FFUART 1
/* allow to overwrite serial and ethaddr */
@@
-108,7
+111,7
@@
#else
#else
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_
SAVE
ENV
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C
@@
-131,8
+134,6
@@
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-#define LITTLEENDIAN 1 /* used by usb_ohci.c */
-
#define CONFIG_BOOTDELAY -1
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_BOOTDELAY -1
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.0.0
@@
-169,11
+170,9
@@
#define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-#define CONFIG_SYS_HZ
3250000 /* incrementer freq: 3.25 MHz */
+#define CONFIG_SYS_HZ
1000
/* Monahans Core Frequency */
#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
/* Monahans Core Frequency */
#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
@@
-183,7
+182,11
@@
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* #define CONFIG_SYS_MMC_BASE 0xF0000000 */
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#endif
/*
* Stack sizes
/*
* Stack sizes
@@
-258,7
+261,6
@@
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_SYS_NO_FLASH 1