+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS (0xC << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+#define CONFIG_HAS_DATAFLASH 1
+#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
+#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
+
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+#undef CONFIG_ENV_IS_IN_DATAFLASH
+
+#ifdef CONFIG_ENV_IS_IN_DATAFLASH
+#define CONFIG_ENV_OFFSET 0x20000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
+#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
+#else
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
+#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_ENV_IS_IN_DATAFLASH */