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tegra: fdt: Enable FDT support for Seaboard
[oweals/u-boot.git]
/
include
/
configs
/
aria.h
diff --git
a/include/configs/aria.h
b/include/configs/aria.h
index 4211113d9e136494c7afdb0eb3e10f914ed71560..c9f0076ee6a177f67f9e10ce0d5e64c7ac249ebe 100644
(file)
--- a/
include/configs/aria.h
+++ b/
include/configs/aria.h
@@
-49,7
+49,8
@@
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
-#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
/* video */
#undef CONFIG_VIDEO
/* video */
#undef CONFIG_VIDEO
@@
-78,6
+79,9
@@
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#define CONFIG_SYS_DDR_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#define CONFIG_SYS_DDR_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
/* DDR Controller Configuration
*
/* DDR Controller Configuration
*
@@
-126,7
+130,7
@@
#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
(1 << 30) | /* CKE */ \
(1 << 29) | /* CLK_ON */ \
#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
(1 << 30) | /* CKE */ \
(1 << 29) | /* CLK_ON */ \
- (
1
<< 28) | /* CMD_MODE */ \
+ (
0
<< 28) | /* CMD_MODE */ \
(4 << 25) | /* DRAM_ROW_SELECT */ \
(3 << 21) | /* DRAM_BANK_SELECT */ \
(0 << 18) | /* SELF_REF_EN */ \
(4 << 25) | /* DRAM_ROW_SELECT */ \
(3 << 21) | /* DRAM_BANK_SELECT */ \
(0 << 18) | /* SELF_REF_EN */ \
@@
-143,16
+147,12
@@
(0 << 0) /* FIFO_UV_EN */ \
)
(0 << 0) /* FIFO_UV_EN */ \
)
-#define CONFIG_SYS_MDDRC_
SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28))
+#define CONFIG_SYS_MDDRC_
TIME_CFG0 0x030C3D2E
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
-#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E
-
-#define CONFIG_SYS_MICRON_NOP 0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
+#define CONFIG_SYS_DDRCMD_NOP 0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
(0 << 22) | /* DRAM_CS */ \
(0 << 21) | /* DRAM_RAS */ \
#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
(0 << 22) | /* DRAM_CS */ \
(0 << 21) | /* DRAM_RAS */ \
@@
-172,7
+172,7
@@
)
#define CONFIG_SYS_MICRON_EMR2 0x01020000
#define CONFIG_SYS_MICRON_EMR3 0x01030000
)
#define CONFIG_SYS_MICRON_EMR2 0x01020000
#define CONFIG_SYS_MICRON_EMR3 0x01030000
-#define CONFIG_SYS_
MICRON
_RFSH 0x01080000
+#define CONFIG_SYS_
DDRCMD
_RFSH 0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
(0 << 22) | /* DRAM_CS */ \
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
(0 << 22) | /* DRAM_CS */ \
@@
-194,12
+194,12
@@
/*
* Backward compatible definitions,
/*
* Backward compatible definitions,
- * so we do not have to change cpu/mpc512x/fixed_sdram.c
+ * so we do not have to change
arch/powerpc/
cpu/mpc512x/fixed_sdram.c
*/
*/
-#define CONFIG_SYS_
MICRON
_EM2 (CONFIG_SYS_MICRON_EMR2)
-#define CONFIG_SYS_
MICRON
_EM3 (CONFIG_SYS_MICRON_EMR3)
-#define CONFIG_SYS_
MICRON
_EN_DLL (CONFIG_SYS_MICRON_EMR)
-#define CONFIG_SYS_
MICRON
_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
+#define CONFIG_SYS_
DDRCMD
_EM2 (CONFIG_SYS_MICRON_EMR2)
+#define CONFIG_SYS_
DDRCMD
_EM3 (CONFIG_SYS_MICRON_EMR3)
+#define CONFIG_SYS_
DDRCMD
_EN_DLL (CONFIG_SYS_MICRON_EMR)
+#define CONFIG_SYS_
DDRCMD
_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
@@
-247,15
+247,9
@@
*/
#define CONFIG_CMD_NAND /* enable NAND support */
#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
*/
#define CONFIG_CMD_NAND /* enable NAND support */
#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
-
-
#define CONFIG_NAND_MPC5121_NFC
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_NAND_MPC5121_NFC
#define CONFIG_SYS_NAND_BASE 0x40000000
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*
* Configuration parameters for MPC5121 NAND driver
/*
* Configuration parameters for MPC5121 NAND driver
@@
-301,14
+295,13
@@
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_
END
CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_
SIZE
CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_
TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#ifdef CONFIG_FSL_DIU_FB
@@
-324,7
+317,6
@@
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
/*
* Serial console configuration
/*
* Serial console configuration
@@
-402,7
+394,6
@@
* Ethernet configuration
*/
#define CONFIG_MPC512x_FEC 1
* Ethernet configuration
*/
#define CONFIG_MPC512x_FEC 1
-#define CONFIG_NET_MULTI
#define CONFIG_PHY_ADDR 0x17
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_FEC_AN_TIMEOUT 1
#define CONFIG_PHY_ADDR 0x17
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_FEC_AN_TIMEOUT 1
@@
-510,10
+501,10
@@
/*
* For booting Linux, the board info and command line data
/*
* For booting Linux, the board info and command line data
- * have to be in the first
8
MB of memory, since this is
+ * have to be in the first
256
MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (
8
<< 20)
+#define CONFIG_SYS_BOOTMAPSZ (
256
<< 20)
/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE 32768
/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE 32768
@@
-529,14
+520,6
@@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
@@
-549,8
+532,8
@@
#define CONFIG_TIMESTAMP
#define CONFIG_HOSTNAME aria
#define CONFIG_TIMESTAMP
#define CONFIG_HOSTNAME aria
-#define CONFIG_BOOTFILE
aria/uImage
-#define CONFIG_ROOTPATH
/opt/eldk/ppc_6xx
+#define CONFIG_BOOTFILE
"aria/uImage"
+#define CONFIG_ROOTPATH
"/opt/eldk/ppc_6xx"
#define CONFIG_LOADADDR 400000 /* default load addr */
#define CONFIG_LOADADDR 400000 /* default load addr */