#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDR_SIZE 512
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDR_SIZE 512
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
- OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 \
+ | BR_MS_GPCM \
+ | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_FEC1_PHY_NORXERR
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_FEC1_PHY_NORXERR
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_RW \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_IBAT4U 0
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT4U 0
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_RW \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (0xF0000000 \
+ | BATL_PP_RW \
+ | BATL_MEMCOHERENCE \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U (0xF0000000 \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
-#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
- then source ${script_addr}; \
- else source ${script_addr2}; \
- fi;"
+#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
+ "then source ${script_addr}; " \
+ "else source ${script_addr2}; " \
+ "fi;"
"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \