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Blackfin: bf548-ezkit: bump SPI flash size up
[oweals/u-boot.git]
/
include
/
configs
/
MPC8360ERDK.h
diff --git
a/include/configs/MPC8360ERDK.h
b/include/configs/MPC8360ERDK.h
index 477a1c5821f628731719465568fe4bed1fa1bab8..fc53ecc67a11c73d641628960c2f61d2b5d7acd3 100644
(file)
--- a/
include/configs/MPC8360ERDK.h
+++ b/
include/configs/MPC8360ERDK.h
@@
-22,7
+22,7
@@
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC83
XX 1 /* MPC83XX
family */
+#define CONFIG_MPC83
xx 1 /* MPC83xx
family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
@@
-177,7
+177,8
@@
/*
* Local Bus Configuration & Clock Setup
*/
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
@@
-236,7
+237,6
@@
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@
-249,6
+249,7
@@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
@@
-265,7
+266,6
@@
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
@@
-277,7
+277,6
@@
* Addresses are mapped 1-1.
*/
#define CONFIG_PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI 1
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
@@
-309,7
+308,7
@@
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "
FSL
UEC0"
+#define CONFIG_ETHPRIME "UEC0"
#define CONFIG_UEC_ETH1 /* GETH1 */
#define CONFIG_UEC_ETH1 /* GETH1 */
@@
-319,7
+318,8
@@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 2
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 2
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
@@
-330,7
+330,8
@@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
/*
#endif
/*
@@
-402,16
+403,17
@@
/*
* For booting Linux, the board info and command line data
/*
* For booting Linux, the board info and command line data
- * have to be in the first
8
MB of memory, since this is
+ * have to be in the first
256
MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (
8
<< 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (
256
<< 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
#define CONFIG_SYS_HID2 HID2_HBE
/*
@@
-505,10
+507,6
@@
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
-#define CONFIG_ETHADDR 00:04:9f:ef:01:01
-#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
-#define CONFIG_ETH2ADDR 00:04:9f:ef:01:03
-#define CONFIG_ETH3ADDR 00:04:9f:ef:01:04
#endif
#define CONFIG_BAUDRATE 115200
#endif
#define CONFIG_BAUDRATE 115200
@@
-517,10
+515,6
@@
#define CONFIG_HOSTNAME mpc8360erdk
#define CONFIG_BOOTFILE uImage
#define CONFIG_HOSTNAME mpc8360erdk
#define CONFIG_BOOTFILE uImage
-#define CONFIG_IPADDR 10.0.0.99
-#define CONFIG_SERVERIP 10.0.0.2
-#define CONFIG_GATEWAYIP 10.0.0.2
-#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_ROOTPATH /nfsroot/
#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
#define CONFIG_ROOTPATH /nfsroot/
#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
@@
-531,7
+525,7
@@
"consoledev=ttyS0\0"\
"loadaddr=a00000\0"\
"fdtaddr=900000\0"\
"consoledev=ttyS0\0"\
"loadaddr=a00000\0"\
"fdtaddr=900000\0"\
- "fdtfile=dtb\0"\
+ "fdtfile=
mpc836x_rdk.
dtb\0"\
"fsfile=fs\0"\
"ubootfile=u-boot.bin\0"\
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
"fsfile=fs\0"\
"ubootfile=u-boot.bin\0"\
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\