+
+#define CFG_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CFG_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \
+ ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (10 << TIMING_CFG1_REFREC_SHIFT) | \
+ ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CFG_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+ (0 << TIMING_CFG2_CPO_SHIFT))
+
+#define CFG_DDR_TIMING_3 0x00000000