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Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next
[oweals/u-boot.git]
/
include
/
configs
/
A3000.h
diff --git
a/include/configs/A3000.h
b/include/configs/A3000.h
index ca9592c23bcbd08f5361bd20a928038fa957a2dd..dba1bf727d23f6e764609a943c20c92376a9b0ff 100644
(file)
--- a/
include/configs/A3000.h
+++ b/
include/configs/A3000.h
@@
-52,23
+52,20
@@
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTDELAY 5
-#if 0
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_FLASH | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_NET | \
- CFG_CMD_PCI )
-#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
/*
/*
@@
-90,7
+87,7
@@
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef
CONFIG_SOFT_I2C
/* I2C bit-banged */
+#undef
CONFIG_SOFT_I2C
/* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
@@
-98,9
+95,9
@@
* PCI stuff
*-----------------------------------------------------------------------
*/
* PCI stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
/* print pci devices @ startup */
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
@@
-123,11
+120,11
@@
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE
0x00000000
-#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE
CFG_FLASH_BASE0_PRELIM
+#define CFG_FLASH_BASE0_PRELIM
0xFF000000 /* FLASH bank on RCS#0 */
+#define CFG_FLASH_BASE1_PRELIM
0xFF000000 /* FLASH bank on RCS#1 */
+#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM }
/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM }
/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
@@
-173,7
+170,7
@@
* Definitions for initial stack pointer and data area
*/
* Definitions for initial stack pointer and data area
*/
-/* #define CFG_MONITOR_BASE
TEXT_BASE */
+/* #define CFG_MONITOR_BASE TEXT_BASE */
/*#define CFG_GBL_DATA_SIZE 256*/
#define CFG_GBL_DATA_SIZE 128
#define CFG_INIT_RAM_ADDR 0x40000000
/*#define CFG_GBL_DATA_SIZE 256*/
#define CFG_GBL_DATA_SIZE 128
#define CFG_INIT_RAM_ADDR 0x40000000
@@
-195,7
+192,7
@@
*/
#define CFG_ROMNAL 7
#define CFG_ROMFAL 11
*/
#define CFG_ROMNAL 7
#define CFG_ROMFAL 11
-#define CFG_DBUS_SIZE
0x3
+#define CFG_DBUS_SIZE 0x3
/* Bit-field values for MCCR2.
*/
/* Bit-field values for MCCR2.
*/
@@
-221,7
+218,7
@@
#define CFG_EXTROM 1
#define CFG_REGDIMM 0
#define CFG_EXTROM 1
#define CFG_REGDIMM 0
-#define CFG_PGMAX
0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
@@
-309,7
+306,7
@@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if
(CONFIG_COMMANDS & CF
G_CMD_KGDB)
+#if
defined(CONFI
G_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif