-#define intc XPAR_INTC_0_BASEADDR
-#define ISR (intc+(0*4)) /* Interrupt Status Register */
-#define IPR (intc+(1*4)) /* Interrupt Pending Register */
-#define IER (intc+(2*4)) /* Interrupt Enable Register */
-#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */
-#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */
-#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */
-#define IVR (intc+(6*4)) /* Interrupt Vector Register */
-#define MER (intc+(7*4)) /* Master Enable Register */
+#define intc XPAR_INTC_0_BASEADDR
+#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
+#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
+#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
+#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
+#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
+#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
+#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
+#define MER (intc + (7 * 4)) /* Master Enable Register */