- char res1[16];
- uint ievent; /* 0x24010 - Interrupt Event Register */
- uint imask; /* 0x24014 - Interrupt Mask Register */
- uint edis; /* 0x24018 - Error Disabled Register */
- char res2[4];
- uint ecntrl; /* 0x24020 - Ethernet Control Register */
- uint minflr; /* 0x24024 - Minimum Frame Length Register */
- uint ptv; /* 0x24028 - Pause Time Value Register */
- uint dmactrl; /* 0x2402c - DMA Control Register */
- uint tbipa; /* 0x24030 - TBI PHY Address Register */
- char res3[88];
- uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
- char res4[8];
- uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
- uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
- char res5[96];
- uint tctrl; /* 0x24100 - Transmit Control Register */
- uint tstat; /* 0x24104 - Transmit Status Register */
- char res6[4];
- uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
- char res7[16];
- uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
- uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
- char res8[88];
- uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
- uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
- char res9[120];
- uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
- uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
- char res10[168];
- uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
- uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
- uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
- uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
- uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
- uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
- uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
- char res11[52];
- uint rctrl; /* 0x24300 - Receive Control Register */
- uint rstat; /* 0x24304 - Receive Status Register */
- char res12[4];
- uint rbdlen; /* 0x2430c - RxBD Data Length Register */
- char res13[16];
- uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
- uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
- char res14[24];
- uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
- uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
- char res15[56];
- uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
- uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
- uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
- uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
- uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
- uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
- uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
- uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
- char res16[96];
- uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
- uint rbase; /* 0x24404 - Receive Descriptor Base Address */
- uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
- uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
- uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
- uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
- uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
- uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
- char res17[224];
- uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
- uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
- uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
- uint hafdup; /* 0x2450c - Half Duplex Register */
- uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
- char res18[12];
- uint miimcfg; /* 0x24520 - MII Management Configuration Register */
- uint miimcom; /* 0x24524 - MII Management Command Register */
- uint miimadd; /* 0x24528 - MII Management Address Register */
- uint miimcon; /* 0x2452c - MII Management Control Register */
- uint miimstat; /* 0x24530 - MII Management Status Register */
- uint miimind; /* 0x24534 - MII Management Indicator Register */
- char res19[4];
- uint ifstat; /* 0x2453c - Interface Status Register */
- uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
- uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
- char res20[312];
- uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
- uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
- uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
- uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
- uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
- uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
- uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
- uint rbyt; /* 0x2469c - Receive Byte Counter */
- uint rpkt; /* 0x246a0 - Receive Packet Counter */
- uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
- uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
- uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
- uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
- uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
- uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
- uint raln; /* 0x246bc - Receive Alignment Error Counter */
- uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
- uint rcde; /* 0x246c4 - Receive Code Error Counter */
- uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
- uint rund; /* 0x246cc - Receive Undersize Packet Counter */
- uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
- uint rfrg; /* 0x246d4 - Receive Fragments Counter */
- uint rjbr; /* 0x246d8 - Receive Jabber Counter */
- uint rdrp; /* 0x246dc - Receive Drop Counter */
- uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
- uint tpkt; /* 0x246e4 - Transmit Packet Counter */
- uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
- uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
- uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
- uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
- uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
- uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
- uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
- uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
- uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
- uint tncl; /* 0x2470c - Transmit Total Collision Counter */
- char res21[4];
- uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
- uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
- uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
- uint txcf; /* 0x24720 - Transmit Control Frame Counter */
- uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
- uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
- uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
- uint car1; /* 0x24730 - Carry Register One */
- uint car2; /* 0x24734 - Carry Register Two */
- uint cam1; /* 0x24738 - Carry Mask Register One */
- uint cam2; /* 0x2473c - Carry Mask Register Two */
- char res22[192];
- uint iaddr0; /* 0x24800 - Indivdual address register 0 */
- uint iaddr1; /* 0x24804 - Indivdual address register 1 */
- uint iaddr2; /* 0x24808 - Indivdual address register 2 */
- uint iaddr3; /* 0x2480c - Indivdual address register 3 */
- uint iaddr4; /* 0x24810 - Indivdual address register 4 */
- uint iaddr5; /* 0x24814 - Indivdual address register 5 */
- uint iaddr6; /* 0x24818 - Indivdual address register 6 */
- uint iaddr7; /* 0x2481c - Indivdual address register 7 */
- char res23[96];
- uint gaddr0; /* 0x24880 - Global address register 0 */
- uint gaddr1; /* 0x24884 - Global address register 1 */
- uint gaddr2; /* 0x24888 - Global address register 2 */
- uint gaddr3; /* 0x2488c - Global address register 3 */
- uint gaddr4; /* 0x24890 - Global address register 4 */
- uint gaddr5; /* 0x24894 - Global address register 5 */
- uint gaddr6; /* 0x24898 - Global address register 6 */
- uint gaddr7; /* 0x2489c - Global address register 7 */
- char res24[96];
- uint pmd0; /* 0x24900 - Pattern Match Data Register */
- char res25[4];
- uint pmask0; /* 0x24908 - Pattern Mask Register */
- char res26[4];
- uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
- char res27[4];
- uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
- uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd1; /* 0x24920 - Pattern Match Data Register */
- char res28[4];
- uint pmask1; /* 0x24928 - Pattern Mask Register */
- char res29[4];
- uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
- char res30[4];
- uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
- uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd2; /* 0x24940 - Pattern Match Data Register */
- char res31[4];
- uint pmask2; /* 0x24948 - Pattern Mask Register */
- char res32[4];
- uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
- char res33[4];
- uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
- uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd3; /* 0x24960 - Pattern Match Data Register */
- char res34[4];
- uint pmask3; /* 0x24968 - Pattern Mask Register */
- char res35[4];
- uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
- char res36[4];
- uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
- uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd4; /* 0x24980 - Pattern Match Data Register */
- char res37[4];
- uint pmask4; /* 0x24988 - Pattern Mask Register */
- char res38[4];
- uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
- char res39[4];
- uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
- uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd5; /* 0x249a0 - Pattern Match Data Register */
- char res40[4];
- uint pmask5; /* 0x249a8 - Pattern Mask Register */
- char res41[4];
- uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
- char res42[4];
- uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
- uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd6; /* 0x249c0 - Pattern Match Data Register */
- char res43[4];
- uint pmask6; /* 0x249c8 - Pattern Mask Register */
- char res44[4];
- uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
- char res45[4];
- uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
- uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd7; /* 0x249e0 - Pattern Match Data Register */
- char res46[4];
- uint pmask7; /* 0x249e8 - Pattern Mask Register */
- char res47[4];
- uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
- char res48[4];
- uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
- uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd8; /* 0x24a00 - Pattern Match Data Register */
- char res49[4];
- uint pmask8; /* 0x24a08 - Pattern Mask Register */
- char res50[4];
- uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
- char res51[4];
- uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
- uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd9; /* 0x24a20 - Pattern Match Data Register */
- char res52[4];
- uint pmask9; /* 0x24a28 - Pattern Mask Register */
- char res53[4];
- uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
- char res54[4];
- uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
- uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd10; /* 0x24a40 - Pattern Match Data Register */
- char res55[4];
- uint pmask10; /* 0x24a48 - Pattern Mask Register */
- char res56[4];
- uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
- char res57[4];
- uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
- uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd11; /* 0x24a60 - Pattern Match Data Register */
- char res58[4];
- uint pmask11; /* 0x24a68 - Pattern Mask Register */
- char res59[4];
- uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
- char res60[4];
- uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
- uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd12; /* 0x24a80 - Pattern Match Data Register */
- char res61[4];
- uint pmask12; /* 0x24a88 - Pattern Mask Register */
- char res62[4];
- uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
- char res63[4];
- uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
- uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
- char res64[4];
- uint pmask13; /* 0x24aa8 - Pattern Mask Register */
- char res65[4];
- uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
- char res66[4];
- uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
- uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
- char res67[4];
- uint pmask14; /* 0x24ac8 - Pattern Mask Register */
- char res68[4];
- uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
- char res69[4];
- uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
- uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
- uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
- char res70[4];
- uint pmask15; /* 0x24ae8 - Pattern Mask Register */
- char res71[4];
- uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
- char res72[4];
- uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
- uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
- char res73[248];
- uint attr; /* 0x24bf8 - Attributes Register */
- uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
- char res74[1024];
+ u8 res1[16];
+ u32 ievent; /* IRQ Event */
+ u32 imask; /* IRQ Mask */
+ u32 edis; /* Error Disabled */
+ u8 res2[4];
+ u32 ecntrl; /* Ethernet Control */
+ u32 minflr; /* Minimum Frame Len */
+ u32 ptv; /* Pause Time Value */
+ u32 dmactrl; /* DMA Control */
+ u32 tbipa; /* TBI PHY Addr */
+ u8 res3[88];
+ u32 fifo_tx_thr; /* FIFO transmit threshold */
+ u8 res4[8];
+ u32 fifo_tx_starve; /* FIFO transmit starve */
+ u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
+ u8 res5[96];
+ u32 tctrl; /* TX Control */
+ u32 tstat; /* TX Status */
+ u8 res6[4];
+ u32 tbdlen; /* TX Buffer Desc Data Len */
+ u8 res7[16];
+ u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
+ u32 ctbptr; /* Current TX Buffer Desc Ptr */
+ u8 res8[88];
+ u32 tbptrh; /* TX Buffer Desc Ptr High */
+ u32 tbptr; /* TX Buffer Desc Ptr Low */
+ u8 res9[120];
+ u32 tbaseh; /* TX Desc Base Addr High */
+ u32 tbase; /* TX Desc Base Addr */
+ u8 res10[168];
+ u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
+ u32 ostbdp; /* OOS TX Data Buffer Ptr */
+ u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
+ u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
+ u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
+ u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
+ u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
+ u8 res11[52];
+ u32 rctrl; /* RX Control */
+ u32 rstat; /* RX Status */
+ u8 res12[4];
+ u32 rbdlen; /* RxBD Data Len */
+ u8 res13[16];
+ u32 crbptrh; /* Current RX Buffer Desc Ptr High */
+ u32 crbptr; /* Current RX Buffer Desc Ptr */
+ u8 res14[24];
+ u32 mrblr; /* Maximum RX Buffer Len */
+ u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
+ u8 res15[56];
+ u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
+ u32 rbptr; /* RX Buffer Desc Ptr */
+ u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
+ u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
+ u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
+ u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
+ u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
+ u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
+ u8 res16[96];
+ u32 rbaseh; /* RX Desc Base Addr High 0 */
+ u32 rbase; /* RX Desc Base Addr */
+ u32 rbaseh1; /* RX Desc Base Addr High 1 */
+ u32 rbasel1; /* RX Desc Base Addr Low 1 */
+ u32 rbaseh2; /* RX Desc Base Addr High 2 */
+ u32 rbasel2; /* RX Desc Base Addr Low 2 */
+ u32 rbaseh3; /* RX Desc Base Addr High 3 */
+ u32 rbasel3; /* RX Desc Base Addr Low 3 */
+ u8 res17[224];
+ u32 maccfg1; /* MAC Configuration 1 */
+ u32 maccfg2; /* MAC Configuration 2 */
+ u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
+ u32 hafdup; /* Half Duplex */
+ u32 maxfrm; /* Maximum Frame Len */
+ u8 res18[12];
+ u32 miimcfg; /* MII Management Configuration */
+ u32 miimcom; /* MII Management Cmd */
+ u32 miimadd; /* MII Management Addr */
+ u32 miimcon; /* MII Management Control */
+ u32 miimstat; /* MII Management Status */
+ u32 miimind; /* MII Management Indicator */
+ u8 res19[4];
+ u32 ifstat; /* Interface Status */
+ u32 macstnaddr1; /* Station Addr Part 1 */
+ u32 macstnaddr2; /* Station Addr Part 2 */
+ u8 res20[312];
+ u32 tr64; /* TX & RX 64-byte Frame Counter */
+ u32 tr127; /* TX & RX 65-127 byte Frame Counter */
+ u32 tr255; /* TX & RX 128-255 byte Frame Counter */
+ u32 tr511; /* TX & RX 256-511 byte Frame Counter */
+ u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
+ u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
+ u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
+ u32 rbyt; /* RX Byte Counter */
+ u32 rpkt; /* RX Packet Counter */
+ u32 rfcs; /* RX FCS Error Counter */
+ u32 rmca; /* RX Multicast Packet Counter */
+ u32 rbca; /* RX Broadcast Packet Counter */
+ u32 rxcf; /* RX Control Frame Packet Counter */
+ u32 rxpf; /* RX Pause Frame Packet Counter */
+ u32 rxuo; /* RX Unknown OP Code Counter */
+ u32 raln; /* RX Alignment Error Counter */
+ u32 rflr; /* RX Frame Len Error Counter */
+ u32 rcde; /* RX Code Error Counter */
+ u32 rcse; /* RX Carrier Sense Error Counter */
+ u32 rund; /* RX Undersize Packet Counter */
+ u32 rovr; /* RX Oversize Packet Counter */
+ u32 rfrg; /* RX Fragments Counter */
+ u32 rjbr; /* RX Jabber Counter */
+ u32 rdrp; /* RX Drop Counter */
+ u32 tbyt; /* TX Byte Counter Counter */
+ u32 tpkt; /* TX Packet Counter */
+ u32 tmca; /* TX Multicast Packet Counter */
+ u32 tbca; /* TX Broadcast Packet Counter */
+ u32 txpf; /* TX Pause Control Frame Counter */
+ u32 tdfr; /* TX Deferral Packet Counter */
+ u32 tedf; /* TX Excessive Deferral Packet Counter */
+ u32 tscl; /* TX Single Collision Packet Counter */
+ u32 tmcl; /* TX Multiple Collision Packet Counter */
+ u32 tlcl; /* TX Late Collision Packet Counter */
+ u32 txcl; /* TX Excessive Collision Packet Counter */
+ u32 tncl; /* TX Total Collision Counter */
+ u8 res21[4];
+ u32 tdrp; /* TX Drop Frame Counter */
+ u32 tjbr; /* TX Jabber Frame Counter */
+ u32 tfcs; /* TX FCS Error Counter */
+ u32 txcf; /* TX Control Frame Counter */
+ u32 tovr; /* TX Oversize Frame Counter */
+ u32 tund; /* TX Undersize Frame Counter */
+ u32 tfrg; /* TX Fragments Frame Counter */
+ u32 car1; /* Carry One */
+ u32 car2; /* Carry Two */
+ u32 cam1; /* Carry Mask One */
+ u32 cam2; /* Carry Mask Two */
+ u8 res22[192];
+ u32 iaddr0; /* Indivdual addr 0 */
+ u32 iaddr1; /* Indivdual addr 1 */
+ u32 iaddr2; /* Indivdual addr 2 */
+ u32 iaddr3; /* Indivdual addr 3 */
+ u32 iaddr4; /* Indivdual addr 4 */
+ u32 iaddr5; /* Indivdual addr 5 */
+ u32 iaddr6; /* Indivdual addr 6 */
+ u32 iaddr7; /* Indivdual addr 7 */
+ u8 res23[96];
+ u32 gaddr0; /* Global addr 0 */
+ u32 gaddr1; /* Global addr 1 */
+ u32 gaddr2; /* Global addr 2 */
+ u32 gaddr3; /* Global addr 3 */
+ u32 gaddr4; /* Global addr 4 */
+ u32 gaddr5; /* Global addr 5 */
+ u32 gaddr6; /* Global addr 6 */
+ u32 gaddr7; /* Global addr 7 */
+ u8 res24[96];
+ u32 pmd0; /* Pattern Match Data */
+ u8 res25[4];
+ u32 pmask0; /* Pattern Mask */
+ u8 res26[4];
+ u32 pcntrl0; /* Pattern Match Control */
+ u8 res27[4];
+ u32 pattrb0; /* Pattern Match Attrs */
+ u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd1; /* Pattern Match Data */
+ u8 res28[4];
+ u32 pmask1; /* Pattern Mask */
+ u8 res29[4];
+ u32 pcntrl1; /* Pattern Match Control */
+ u8 res30[4];
+ u32 pattrb1; /* Pattern Match Attrs */
+ u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd2; /* Pattern Match Data */
+ u8 res31[4];
+ u32 pmask2; /* Pattern Mask */
+ u8 res32[4];
+ u32 pcntrl2; /* Pattern Match Control */
+ u8 res33[4];
+ u32 pattrb2; /* Pattern Match Attrs */
+ u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd3; /* Pattern Match Data */
+ u8 res34[4];
+ u32 pmask3; /* Pattern Mask */
+ u8 res35[4];
+ u32 pcntrl3; /* Pattern Match Control */
+ u8 res36[4];
+ u32 pattrb3; /* Pattern Match Attrs */
+ u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd4; /* Pattern Match Data */
+ u8 res37[4];
+ u32 pmask4; /* Pattern Mask */
+ u8 res38[4];
+ u32 pcntrl4; /* Pattern Match Control */
+ u8 res39[4];
+ u32 pattrb4; /* Pattern Match Attrs */
+ u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd5; /* Pattern Match Data */
+ u8 res40[4];
+ u32 pmask5; /* Pattern Mask */
+ u8 res41[4];
+ u32 pcntrl5; /* Pattern Match Control */
+ u8 res42[4];
+ u32 pattrb5; /* Pattern Match Attrs */
+ u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd6; /* Pattern Match Data */
+ u8 res43[4];
+ u32 pmask6; /* Pattern Mask */
+ u8 res44[4];
+ u32 pcntrl6; /* Pattern Match Control */
+ u8 res45[4];
+ u32 pattrb6; /* Pattern Match Attrs */
+ u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd7; /* Pattern Match Data */
+ u8 res46[4];
+ u32 pmask7; /* Pattern Mask */
+ u8 res47[4];
+ u32 pcntrl7; /* Pattern Match Control */
+ u8 res48[4];
+ u32 pattrb7; /* Pattern Match Attrs */
+ u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd8; /* Pattern Match Data */
+ u8 res49[4];
+ u32 pmask8; /* Pattern Mask */
+ u8 res50[4];
+ u32 pcntrl8; /* Pattern Match Control */
+ u8 res51[4];
+ u32 pattrb8; /* Pattern Match Attrs */
+ u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd9; /* Pattern Match Data */
+ u8 res52[4];
+ u32 pmask9; /* Pattern Mask */
+ u8 res53[4];
+ u32 pcntrl9; /* Pattern Match Control */
+ u8 res54[4];
+ u32 pattrb9; /* Pattern Match Attrs */
+ u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd10; /* Pattern Match Data */
+ u8 res55[4];
+ u32 pmask10; /* Pattern Mask */
+ u8 res56[4];
+ u32 pcntrl10; /* Pattern Match Control */
+ u8 res57[4];
+ u32 pattrb10; /* Pattern Match Attrs */
+ u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd11; /* Pattern Match Data */
+ u8 res58[4];
+ u32 pmask11; /* Pattern Mask */
+ u8 res59[4];
+ u32 pcntrl11; /* Pattern Match Control */
+ u8 res60[4];
+ u32 pattrb11; /* Pattern Match Attrs */
+ u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd12; /* Pattern Match Data */
+ u8 res61[4];
+ u32 pmask12; /* Pattern Mask */
+ u8 res62[4];
+ u32 pcntrl12; /* Pattern Match Control */
+ u8 res63[4];
+ u32 pattrb12; /* Pattern Match Attrs */
+ u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd13; /* Pattern Match Data */
+ u8 res64[4];
+ u32 pmask13; /* Pattern Mask */
+ u8 res65[4];
+ u32 pcntrl13; /* Pattern Match Control */
+ u8 res66[4];
+ u32 pattrb13; /* Pattern Match Attrs */
+ u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd14; /* Pattern Match Data */
+ u8 res67[4];
+ u32 pmask14; /* Pattern Mask */
+ u8 res68[4];
+ u32 pcntrl14; /* Pattern Match Control */
+ u8 res69[4];
+ u32 pattrb14; /* Pattern Match Attrs */
+ u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd15; /* Pattern Match Data */
+ u8 res70[4];
+ u32 pmask15; /* Pattern Mask */
+ u8 res71[4];
+ u32 pcntrl15; /* Pattern Match Control */
+ u8 res72[4];
+ u32 pattrb15; /* Pattern Match Attrs */
+ u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
+ u8 res73[248];
+ u32 attr; /* Attrs */
+ u32 attreli; /* Attrs Extract Len & Idx */
+ u8 res74[1024];