+
+/*********************************************************************
+* PLL Clock Module
+*********************************************************************/
+/* Bit definitions and macros for PLL_SYNCR */
+#define PLL_SYNCR_LOLRE (0x8000)
+#define PLL_SYNCR_MFD2 (0x4000)
+#define PLL_SYNCR_MFD1 (0x2000)
+#define PLL_SYNCR_MFD0 (0x1000)
+#define PLL_SYNCR_LOCRE (0x0800)
+#define PLL_SYNCR_RFC2 (0x0400)
+#define PLL_SYNCR_RFC1 (0x0200)
+#define PLL_SYNCR_RFC0 (0x0100)
+#define PLL_SYNCR_LOCEN (0x0080)
+#define PLL_SYNCR_DISCLK (0x0040)
+#define PLL_SYNCR_FWKUP (0x0020)
+#define PLL_SYNCR_STPMD1 (0x0008)
+#define PLL_SYNCR_STPMD0 (0x0004)
+
+/* Bit definitions and macros for PLL_SYNSR */
+#define PLL_SYNSR_MODE (0x0080)
+#define PLL_SYNSR_PLLSEL (0x0040)
+#define PLL_SYNSR_PLLREF (0x0020)
+#define PLL_SYNSR_LOCKS (0x0010)
+#define PLL_SYNSR_LOCK (0x0008)
+#define PLL_SYNSR_LOCS (0x0004)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM_SWT1 (8)
+#define INT0_LO_DMA_00 (9)
+#define INT0_LO_DMA_01 (10)
+#define INT0_LO_DMA_02 (11)
+#define INT0_LO_DMA_03 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC_TXF (23)
+#define INT0_LO_FEC_TXB (24)
+#define INT0_LO_FEC_UN (25)
+#define INT0_LO_FEC_RL (26)
+#define INT0_LO_FEC_RXF (27)
+#define INT0_LO_FEC_RXB (28)
+#define INT0_LO_FEC_MII (29)
+#define INT0_LO_FEC_LC (30)
+#define INT0_LO_FEC_HBERR (31)
+#define INT0_HI_FEC_GRA (32)
+#define INT0_HI_FEC_EBERR (33)
+#define INT0_HI_FEC_BABT (34)
+#define INT0_HI_FEC_BABR (35)
+#define INT0_HI_PMM_LVDF (36)
+#define INT0_HI_QADC_CF1 (37)
+#define INT0_HI_QADC_CF2 (38)
+#define INT0_HI_QADC_PF1 (39)
+#define INT0_HI_QADC_PF2 (40)
+#define INT0_HI_GPTA_TOF (41)
+#define INT0_HI_GPTA_PAIF (42)
+#define INT0_HI_GPTA_PAOVF (43)
+#define INT0_HI_GPTA_C0F (44)
+#define INT0_HI_GPTA_C1F (45)
+#define INT0_HI_GPTA_C2F (46)
+#define INT0_HI_GPTA_C3F (47)
+#define INT0_HI_GPTB_TOF (48)
+#define INT0_HI_GPTB_PAIF (49)
+#define INT0_HI_GPTB_PAOVF (50)
+#define INT0_HI_GPTB_C0F (51)
+#define INT0_HI_GPTB_C1F (52)
+#define INT0_HI_GPTB_C2F (53)
+#define INT0_HI_GPTB_C3F (54)
+#define INT0_HI_PIT0 (55)
+#define INT0_HI_PIT1 (56)
+#define INT0_HI_PIT2 (57)
+#define INT0_HI_PIT3 (58)
+#define INT0_HI_CFM_CBEIF (59)
+#define INT0_HI_CFM_CCIF (60)
+#define INT0_HI_CFM_PVIF (61)
+#define INT0_HI_CFM_AEIF (62)