+ /* setup display pll for requested clock frequency */
+ err = panel->pxl_clk;
+ err_r = err;
+
+ for (d = 2; d < 255; d++) {
+ for (m = 2; m < 2047; m++) {
+ if ((V_OSCK * m) < (panel->pxl_clk * d))
+ continue;
+ n = (V_OSCK * m) / (panel->pxl_clk * d);
+ if (n > 127)
+ break;
+ if (((V_OSCK * m) / n) > LCDC_FMAX)
+ break;
+
+ err = abs((V_OSCK * m) / n / d - panel->pxl_clk);
+ if (err < err_r) {
+ err_r = err;
+ dpll_disp.m = m;
+ dpll_disp.n = n;
+ best_d = d;
+ }
+ }
+ }
+ debug("%s: PLL: best error %d Hz (M %d, N %d, DISP %d)\n",
+ __func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
+ do_setup_dpll(&dpll_disp_regs, &dpll_disp);
+
+ /* clock source for LCDC from dispPLL M2 */
+ writel(0x0, &cmdpll->clklcdcpixelclk);
+