- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
- defined(CONFIG_AT91SAM9261)
- /* Enable PLLB */
- writel(get_pllb_init(), &pmc->pllbr);
- while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
- ;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
- defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3)
- /* Enable UPLL */
- writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN,
- &pmc->uckr);
- while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU)
- ;
-
- /* Select PLLA as input clock of OHCI */
- writel(AT91_PMC_USBS_USB_UPLL | AT91_PMC_USBDIV_10, &pmc->usb);
+#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
+ if (at91_pllb_clk_enable(get_pllb_init()))
+ return -1;
+
+#ifdef CONFIG_AT91SAM9N12
+ at91_usb_clk_init(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2);