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spi: cadence_qspi: Add quad write support
[oweals/u-boot.git]
/
drivers
/
spi
/
rk_spi.c
diff --git
a/drivers/spi/rk_spi.c
b/drivers/spi/rk_spi.c
index c70d63627704cfded3d481128a555d88f7f4ed49..14437c0a9afe65808786fea09109f97dbef94680 100644
(file)
--- a/
drivers/spi/rk_spi.c
+++ b/
drivers/spi/rk_spi.c
@@
-1,3
+1,4
@@
+// SPDX-License-Identifier: GPL-2.0+
/*
* spi driver for rockchip
*
/*
* spi driver for rockchip
*
@@
-5,8
+6,6
@@
*
* (C) Copyright 2008-2013 Rockchip Electronics
* Peter, Software Engineering, <superpeter.cai@gmail.com>.
*
* (C) Copyright 2008-2013 Rockchip Electronics
* Peter, Software Engineering, <superpeter.cai@gmail.com>.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
*/
#include <common.h>
@@
-22,8
+21,6
@@
#include <dm/pinctrl.h>
#include "rk_spi.h"
#include <dm/pinctrl.h>
#include "rk_spi.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
@@
-94,7
+91,7
@@
static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
*/
if (clk_div > 0xfffe) {
clk_div = 0xfffe;
*/
if (clk_div > 0xfffe) {
clk_div = 0xfffe;
- debug("%s: can't divide down to %d
hz (actual will be %d h
z)\n",
+ debug("%s: can't divide down to %d
Hz (actual will be %d H
z)\n",
__func__, speed, priv->input_rate / clk_div);
}
__func__, speed, priv->input_rate / clk_div);
}
@@
-184,7
+181,7
@@
static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
- plat->base = dev
fdt_get
_addr(bus);
+ plat->base = dev
_read
_addr(bus);
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {