+static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
+{
+ uint32_t confr, div = 0;
+
+ confr = readl(&priv->regs->channel[priv->cs].chconf);
+
+ /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
+ if (priv->freq) {
+ while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
+ > priv->freq)
+ div++;
+ } else {
+ div = 0xC;
+ }
+
+ /* set clock divisor */
+ confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
+ confr |= div << 2;
+
+ omap3_spi_write_chconf(priv, confr);
+}
+
+static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
+{
+ uint32_t confr;
+
+ confr = readl(&priv->regs->channel[priv->cs].chconf);
+
+ /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
+ * REVISIT: this controller could support SPI_3WIRE mode.
+ */
+ if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
+ confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+ confr |= OMAP3_MCSPI_CHCONF_DPE0;
+ } else {
+ confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
+ confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
+ }
+
+ /* set SPI mode 0..3 */
+ confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
+ if (priv->mode & SPI_CPHA)
+ confr |= OMAP3_MCSPI_CHCONF_PHA;
+ if (priv->mode & SPI_CPOL)
+ confr |= OMAP3_MCSPI_CHCONF_POL;
+
+ /* set chipselect polarity; manage with FORCE */
+ if (!(priv->mode & SPI_CS_HIGH))
+ confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
+ else
+ confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
+
+ /* Transmit & receive mode */
+ confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+
+ omap3_spi_write_chconf(priv, confr);
+}
+
+static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
+{
+ unsigned int confr;
+
+ /* McSPI individual channel configuration */
+ confr = readl(&priv->regs->channel[priv->cs].chconf);
+
+ /* wordlength */
+ confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
+ confr |= (priv->wordlen - 1) << 7;
+
+ omap3_spi_write_chconf(priv, confr);
+}
+
+static void spi_reset(struct mcspi *regs)
+{
+ unsigned int tmp;
+
+ writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig);
+ do {
+ tmp = readl(®s->sysstatus);
+ } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
+
+ writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
+ OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
+ OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig);
+
+ writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable);
+}
+
+static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
+{
+ unsigned int conf;
+ /*
+ * setup when switching from (reset default) slave mode
+ * to single-channel master mode
+ */
+ conf = readl(&priv->regs->modulctrl);
+ conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
+ conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
+
+ writel(conf, &priv->regs->modulctrl);
+}
+
+#ifndef CONFIG_DM_SPI
+
+static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct omap3_spi_priv, slave);
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct omap3_spi_priv *priv = to_omap3_spi(slave);
+
+ free(priv);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct omap3_spi_priv *priv = to_omap3_spi(slave);
+
+ spi_reset(priv->regs);
+
+ _omap3_spi_claim_bus(priv);
+ _omap3_spi_set_wordlen(priv);
+ _omap3_spi_set_mode(priv);
+ _omap3_spi_set_speed(priv);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct omap3_spi_priv *priv = to_omap3_spi(slave);
+
+ writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct omap3_spi_priv *priv;
+ struct mcspi *regs;
+
+ /*
+ * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
+ * with different number of chip selects (CS, channels):
+ * McSPI1 has 4 CS (bus 0, cs 0 - 3)
+ * McSPI2 has 2 CS (bus 1, cs 0 - 1)
+ * McSPI3 has 2 CS (bus 2, cs 0 - 1)
+ * McSPI4 has 1 CS (bus 3, cs 0)
+ */
+
+ switch (bus) {
+ case 0:
+ regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
+ break;
+#ifdef OMAP3_MCSPI2_BASE
+ case 1:
+ regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
+ break;
+#endif
+#ifdef OMAP3_MCSPI3_BASE
+ case 2:
+ regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
+ break;
+#endif
+#ifdef OMAP3_MCSPI4_BASE
+ case 3:
+ regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
+ break;
+#endif
+ default:
+ printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus);
+ return NULL;
+ }
+
+ if (((bus == 0) && (cs > 3)) ||
+ ((bus == 1) && (cs > 1)) ||
+ ((bus == 2) && (cs > 1)) ||
+ ((bus == 3) && (cs > 0))) {
+ printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus);
+ return NULL;
+ }
+
+ if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
+ printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n",
+ max_hz);
+ return NULL;
+ }
+
+ if (mode > SPI_MODE_3) {
+ printf("SPI error: unsupported SPI mode %i\n", mode);
+ return NULL;
+ }
+
+ priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
+ if (!priv) {
+ printf("SPI error: malloc of SPI structure failed\n");
+ return NULL;
+ }
+
+ priv->regs = regs;
+ priv->cs = cs;
+ priv->freq = max_hz;
+ priv->mode = mode;
+ priv->wordlen = priv->slave.wordlen;
+#if 0
+ /* Please migrate to DM_SPI support for this feature. */
+ priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+#endif
+
+ return &priv->slave;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)