+
+static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
+{
+ struct mpc8xxx_priv *priv = dev_get_priv(dev);
+ spi8xxx_t *spi = priv->spi;
+ u32 bits, mask, div16, pm;
+ u32 mode;
+ ulong clk;
+
+ clk = priv->clk_rate;
+ if (clk / 64 > speed) {
+ div16 = SPI_MODE_DIV16;
+ clk /= 16;
+ } else {
+ div16 = 0;
+ }
+ pm = (clk - 1)/(4*speed) + 1;
+ if (pm > 16) {
+ dev_err(dev, "requested speed %u too small\n", speed);
+ return -EINVAL;
+ }
+ pm--;
+
+ bits = div16 | (pm << SPI_MODE_PM_SHIFT);
+ mask = SPI_MODE_DIV16 | SPI_MODE_PM_MASK;
+ mode = in_be32(&spi->mode);
+ if ((mode & mask) != bits) {
+ /* Must clear mode[EN] while changing speed. */
+ mode &= ~(mask | SPI_MODE_EN);
+ out_be32(&spi->mode, mode);
+ mode |= bits;
+ out_be32(&spi->mode, mode);
+ mode |= SPI_MODE_EN;
+ out_be32(&spi->mode, mode);
+ }
+
+ debug("requested speed %u, set speed to %lu/(%s4*%u) == %lu\n",
+ speed, priv->clk_rate, div16 ? "16*" : "", pm + 1,
+ clk/(4*(pm + 1)));
+
+ return 0;
+}
+
+static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
+{
+ /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
+ * SPI_CPOL (for clock polarity) should work
+ */
+ return 0;
+}
+
+static const struct dm_spi_ops mpc8xxx_spi_ops = {
+ .xfer = mpc8xxx_spi_xfer,
+ .set_speed = mpc8xxx_spi_set_speed,
+ .set_mode = mpc8xxx_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id mpc8xxx_spi_ids[] = {
+ { .compatible = "fsl,spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mpc8xxx_spi) = {
+ .name = "mpc8xxx_spi",
+ .id = UCLASS_SPI,
+ .of_match = mpc8xxx_spi_ids,
+ .ops = &mpc8xxx_spi_ops,
+ .ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
+ .probe = mpc8xxx_spi_probe,
+ .priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
+};