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spi: xilinx_spi: Fix to configure CPOL, CPHA mask
[oweals/u-boot.git]
/
drivers
/
spi
/
fsl_dspi.c
diff --git
a/drivers/spi/fsl_dspi.c
b/drivers/spi/fsl_dspi.c
index 6476f913c8d73b8892c5942fc21fc26b2c041afa..887edd801a42d1a87662ca7e3f0f036f19e50cc2 100644
(file)
--- a/
drivers/spi/fsl_dspi.c
+++ b/
drivers/spi/fsl_dspi.c
@@
-654,7
+654,7
@@
static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
plat->num_chipselect =
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
plat->num_chipselect =
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
- addr =
fdtdec_get_addr(blob, node, "reg"
);
+ addr =
dev_get_addr(bus
);
if (addr == FDT_ADDR_T_NONE) {
debug("DSPI: Can't get base address or size\n");
return -ENOMEM;
if (addr == FDT_ADDR_T_NONE) {
debug("DSPI: Can't get base address or size\n");
return -ENOMEM;
@@
-664,8
+664,8
@@
static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
plat->speed_hz = fdtdec_get_int(blob,
node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
plat->speed_hz = fdtdec_get_int(blob,
node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
- debug("DSPI: regs=
0x%x
, max-frequency=%d, endianess=%s, num-cs=%d\n",
- plat->regs_addr, plat->speed_hz,
+ debug("DSPI: regs=
%pa
, max-frequency=%d, endianess=%s, num-cs=%d\n",
+
&
plat->regs_addr, plat->speed_hz,
plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
plat->num_chipselect);
plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
plat->num_chipselect);