+}
+
+static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+
+ _stm32_serial_setbrg(plat->base, plat->uart_info,
+ plat->clock_rate, baudrate);
+
+ return 0;
+}
+
+static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
+ u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
+ u32 config = 0;
+ uint parity = SERIAL_GET_PARITY(serial_config);
+ uint bits = SERIAL_GET_BITS(serial_config);
+ uint stop = SERIAL_GET_STOP(serial_config);
+
+ /*
+ * only parity config is implemented, check if other serial settings
+ * are the default one.
+ * (STM32F4 serial IP didn't support parity setting)
+ */
+ if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
+ return -ENOTSUPP; /* not supported in driver*/
+
+ clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
+ /* update usart configuration (uart need to be disable)
+ * PCE: parity check enable
+ * PS : '0' : Even / '1' : Odd
+ * M[1:0] = '00' : 8 Data bits
+ * M[1:0] = '01' : 9 Data bits with parity
+ */
+ switch (parity) {
+ default:
+ case SERIAL_PAR_NONE:
+ config = 0;
+ break;
+ case SERIAL_PAR_ODD:
+ config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
+ break;
+ case SERIAL_PAR_EVEN:
+ config = USART_CR1_PCE | USART_CR1_M0;
+ break;
+ }
+
+ clrsetbits_le32(cr1,
+ USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
+ USART_CR1_M0,
+ config);
+ setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));