-#if defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785)
-# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
-# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
-# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
-# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
-# define LSR_ORER 1
-# define FIFOLEVEL_MASK 0xFF
-#elif defined(CONFIG_CPU_SH7763)
-# if defined(CONFIG_CONS_SCIF2)
-# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
-# define LSR_ORER 1
-# define FIFOLEVEL_MASK 0x1F
-# else
-# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
-# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
-# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
-# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
-# define LSR_ORER 1
-# define FIFOLEVEL_MASK 0xFF
-# endif
-#elif defined(CONFIG_CPU_SH7723)
-# if defined(CONIFG_SCIF_A)
-# define SCLSR SCFSR
-# define LSR_ORER 0x0200
-# define FIFOLEVEL_MASK 0x3F
-#else
-# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
-# define LSR_ORER 1
-# define FIFOLEVEL_MASK 0x1F
-#endif
-#elif defined(CONFIG_CPU_SH7750) || \
- defined(CONFIG_CPU_SH7751) || \
- defined(CONFIG_CPU_SH7722) || \
- defined(CONFIG_CPU_SH7203)
-# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
-# define LSR_ORER 1
-# define FIFOLEVEL_MASK 0x1F
-#elif defined(CONFIG_CPU_SH7720)
-# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
-# define LSR_ORER 0x0200
-# define FIFOLEVEL_MASK 0x1F
-#elif defined(CONFIG_CPU_SH7710) || \
- defined(CONFIG_CPU_SH7712)
-# define SCLSR SCFSR /* SCSSR */
-# define LSR_ORER 1
-# define FIFOLEVEL_MASK 0x1F
-#endif
-
-/* SCBRR register value setting */
-#if defined(CONFIG_CPU_SH7720)
-# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
-#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
-/* SH7723 SCIFA use bus clock. So clock *2 */
-# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
-#else /* Generic SuperH */
-# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
-#endif
-
-#define SCR_RE (1 << 4)
-#define SCR_TE (1 << 5)
-#define FCR_RFRST (1 << 1) /* RFCL */
-#define FCR_TFRST (1 << 2) /* TFCL */
-#define FSR_DR (1 << 0)
-#define FSR_RDF (1 << 1)
-#define FSR_FER (1 << 3)
-#define FSR_BRK (1 << 4)
-#define FSR_FER (1 << 3)
-#define FSR_TEND (1 << 6)
-#define FSR_ER (1 << 7)
-
-/*----------------------------------------------------------------------*/