- u8 ctrl;
-
- ctrl = in_be32(&base->ctrl);
- ctrl &= ~CTRL_RE;
- ctrl &= ~CTRL_TE;
- out_be32(&base->ctrl, ctrl);
-
- out_be32(&base->modir, 0);
- out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
-
- out_be32(&base->match, 0);
-
- /* provide data bits, parity, stop bit, etc */
- _lpuart32_serial_setbrg(base, gd->baudrate);
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
+ struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
+ u32 val, tx_fifo_size;
+
+ lpuart_read32(plat->flags, &base->ctrl, &val);
+ val &= ~CTRL_RE;
+ val &= ~CTRL_TE;
+ lpuart_write32(plat->flags, &base->ctrl, val);
+
+ lpuart_write32(plat->flags, &base->modir, 0);
+
+ lpuart_read32(plat->flags, &base->fifo, &val);
+ tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
+ /* Set the TX water to half of FIFO size */
+ if (tx_fifo_size > 1)
+ tx_fifo_size = tx_fifo_size >> 1;
+
+ /* Set RX water to 0, to be triggered by any receive data */
+ lpuart_write32(plat->flags, &base->water,
+ (tx_fifo_size << WATER_TXWATER_OFF));
+
+ /* Enable TX and RX FIFO */
+ val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
+ lpuart_write32(plat->flags, &base->fifo, val);
+
+ lpuart_write32(plat->flags, &base->match, 0);
+
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
+ _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
+ } else {
+ /* provide data bits, parity, stop bit, etc */
+ _lpuart32_serial_setbrg(dev, gd->baudrate);
+ }