+#ifdef CONFIG_MPC5xxx
+int ps2ser_init(void)
+{
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+ unsigned long baseclk;
+ int div;
+
+ /* reset PSC */
+ psc->command = PSC_SEL_MODE_REG_1;
+
+ /* select clock sources */
+#if defined(CONFIG_MGT5100)
+ psc->psc_clock_select = 0xdd00;
+ baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
+#elif defined(CONFIG_MPC5200)
+ psc->psc_clock_select = 0;
+ baseclk = (gd->ipb_clk + 16) / 32;
+#endif
+
+ /* switch to UART mode */
+ psc->sicr = 0;
+
+ /* configure parity, bit length and so on */
+#if defined(CONFIG_MGT5100)
+ psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
+#elif defined(CONFIG_MPC5200)
+ psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
+#endif
+ psc->mode = PSC_MODE_ONE_STOP;
+
+ /* set up UART divisor */
+ div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
+ psc->ctur = (div >> 8) & 0xff;
+ psc->ctlr = div & 0xff;
+
+ /* disable all interrupts */
+ psc->psc_imr = 0;
+
+ /* reset and enable Rx/Tx */
+ psc->command = PSC_RST_RX;
+ psc->command = PSC_RST_TX;
+ psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
+
+ return (0);
+}
+
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+int ps2ser_init(void)
+{
+ NS16550_t com_port = (NS16550_t)COM_BASE;
+
+ com_port->ier = 0x00;
+ com_port->lcr = LCR_BKSE | LCR_8N1;
+ com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
+ com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
+ com_port->lcr = LCR_8N1;
+ com_port->mcr = (MCR_DTR | MCR_RTS);
+ com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
+
+ return (0);
+}
+
+#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */