+
+ return -EINVAL;
+}
+
+static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
+ int index)
+{
+ struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
+ uint shift;
+ uint mask;
+ u32 *addr;
+ int ret;
+
+ ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
+ &mask);
+ if (ret)
+ return ret;
+ return (readl(addr) & mask) >> shift;
+}
+
+static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
+ int muxval, int flags)
+{
+ struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
+ uint shift, ind = index;
+ uint mask;
+ uint value;
+ u32 *addr;
+ int ret;
+
+ debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
+ ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
+ &mask);
+ if (ret)
+ return ret;
+
+ /*
+ * PMU_GPIO0 registers cannot be selectively written so we cannot use
+ * rk_clrsetreg() here. However, the upper 16 bits are reserved and
+ * are ignored when written, so we can use the same code as for the
+ * other GPIO banks providing that we preserve the value of the other
+ * bits.
+ */
+ value = readl(addr);
+ value &= ~(mask << shift);
+ value |= (mask << (shift + 16)) | (muxval << shift);
+ writel(value, addr);
+
+ /* Handle pullup/pulldown */