- /* Set config */
- if (!(config_val & IMX_NO_PAD_CTL)) {
- if (info->flags & SHARE_MUX_CONF_REG) {
- clrsetbits_le32(info->base + conf_reg,
- ~info->mux_mask, config_val);
- } else {
- writel(config_val, info->base + conf_reg);
+ if (input_val >> 24 == 0xff) {
+ u32 val = input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some
+ * IOMUXC general purpose register, not
+ * regular select input register.
+ */
+ val = readl(info->base + input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, info->base + input_reg);
+ } else if (input_reg) {
+ /*
+ * Regular select input register can never be
+ * at offset 0, and we only print register
+ * value for regular case.
+ */
+ if (info->input_sel_base)
+ writel(input_val,
+ info->input_sel_base +
+ input_reg);
+ else
+ writel(input_val,
+ info->base + input_reg);
+
+ dev_dbg(dev, "select_input: offset 0x%x val "
+ "0x%x\n", input_reg, input_val);