+ if (is_mx6dqp())
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
+#if defined(CONFIG_MX6SX)
+ struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+ /* SSP_EN is not used on MX6SX anymore */
+ setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+ /* Force PCIe PHY reset */
+ setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+ /* Power up PCIe PHY */
+ setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+#else
+ /*
+ * If the bootloader already enabled the link we need some special
+ * handling to get the core back into a state where it is safe to
+ * touch it for configuration. As there is no dedicated reset signal
+ * wired up for MX6QDL, we need to manually force LTSSM into "detect"
+ * state before completely disabling LTSSM, which is a prerequisite
+ * for core configuration.
+ *
+ * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
+ * indication that the bootloader activated the link.
+ */
+ if (is_mx6dq() && prepare_for_boot) {
+ u32 val, gpr1, gpr12;
+
+ gpr1 = readl(&iomuxc_regs->gpr[1]);
+ gpr12 = readl(&iomuxc_regs->gpr[12]);
+ if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
+ (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
+ val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+ val |= PCIE_PL_PFLR_FORCE_LINK;
+
+ imx_pcie_fix_dabt_handler(true);
+ writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
+ imx_pcie_fix_dabt_handler(false);
+
+ gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
+ writel(val, &iomuxc_regs->gpr[12]);
+ }
+ }