-#define PCIE_MEM_SIZE (32 << 20)
-
-#if defined(CONFIG_ARMADA_38X)
-#define PCIE_BASE(if) \
- ((if) == 0 ? \
- MVEBU_REG_PCIE_BASE + 0x40000 : \
- MVEBU_REG_PCIE_BASE + 0x4000 * (if))
-
-/*
- * On A38x MV6820 these PEX ports are supported:
- * 0 - Port 0.0
- * 1 - Port 0.1
- * 2 - Port 0.2
- */
-#define MAX_PEX 3
-static struct mvebu_pcie pcie_bus[MAX_PEX];
-
-static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
- int *mem_target, int *mem_attr)
-{
- u8 port[] = { 0, 1, 2 };
- u8 lane[] = { 0, 0, 0 };
- u8 target[] = { 8, 4, 4 };
- u8 attr[] = { 0xe8, 0xe8, 0xd8 };
-
- pcie->port = port[pex_idx];
- pcie->lane = lane[pex_idx];
- *mem_target = target[pex_idx];
- *mem_attr = attr[pex_idx];
-}
-#else
-#define PCIE_BASE(if) \
- ((if) < 8 ? \
- (MVEBU_REG_PCIE_BASE + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) : \
- (MVEBU_REG_PCIE_BASE + 0x2000 + ((if) % 8) * 0x40000))
-
-/*
- * On AXP MV78460 these PEX ports are supported:
- * 0 - Port 0.0
- * 1 - Port 0.1
- * 2 - Port 0.2
- * 3 - Port 0.3
- * 4 - Port 1.0
- * 5 - Port 1.1
- * 6 - Port 1.2
- * 7 - Port 1.3
- * 8 - Port 2.0
- * 9 - Port 3.0
- */
-#define MAX_PEX 10
-static struct mvebu_pcie pcie_bus[MAX_PEX];
-
-static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
- int *mem_target, int *mem_attr)
-{
- u8 port[] = { 0, 0, 0, 0, 1, 1, 1, 1, 2, 3 };
- u8 lane[] = { 0, 1, 2, 3, 0, 1, 2, 3, 0, 0 };
- u8 target[] = { 4, 4, 4, 4, 8, 8, 8, 8, 4, 8 };
- u8 attr[] = { 0xe8, 0xd8, 0xb8, 0x78,
- 0xe8, 0xd8, 0xb8, 0x78,
- 0xf8, 0xf8 };
-
- pcie->port = port[pex_idx];
- pcie->lane = lane[pex_idx];
- *mem_target = target[pex_idx];
- *mem_attr = attr[pex_idx];
-}
-#endif
-
-static int mvebu_pex_unit_is_x4(int pex_idx)
-{
- int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
- u32 mask = (0x0f << (pex_unit * 8));
-
- return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask;
-}