+
+#define PHY_AUTONEGOTIATE_TIMEOUT 5000
+
+#define PORT_COUNT 11
+#define PORT_MASK ((1 << PORT_COUNT) - 1)
+
+/* Device addresses */
+#define DEVADDR_PHY(p) (p)
+#define DEVADDR_PORT(p) (0x10 + (p))
+#define DEVADDR_SERDES 0x0F
+#define DEVADDR_GLOBAL_1 0x1B
+#define DEVADDR_GLOBAL_2 0x1C
+
+/* SMI indirection registers for multichip addressing mode */
+#define SMI_CMD_REG 0x00
+#define SMI_DATA_REG 0x01
+
+/* Global registers */
+#define GLOBAL1_STATUS 0x00
+#define GLOBAL1_CTRL 0x04
+#define GLOBAL1_MON_CTRL 0x1A
+
+/* Global 2 registers */
+#define GLOBAL2_REG_PHY_CMD 0x18
+#define GLOBAL2_REG_PHY_DATA 0x19
+
+/* Port registers */
+#define PORT_REG_STATUS 0x00
+#define PORT_REG_PHYS_CTRL 0x01
+#define PORT_REG_SWITCH_ID 0x03
+#define PORT_REG_CTRL 0x04
+#define PORT_REG_VLAN_MAP 0x06
+#define PORT_REG_VLAN_ID 0x07
+
+/* Phy registers */
+#define PHY_REG_CTRL1 0x10
+#define PHY_REG_STATUS1 0x11
+#define PHY_REG_PAGE 0x16
+
+/* Serdes registers */
+#define SERDES_REG_CTRL_1 0x10
+
+/* Phy page numbers */
+#define PHY_PAGE_COPPER 0
+#define PHY_PAGE_SERDES 1
+
+/* Register fields */
+#define GLOBAL1_CTRL_SWRESET BIT(15)
+
+#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
+#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
+
+#define PORT_REG_STATUS_LINK BIT(11)
+#define PORT_REG_STATUS_DUPLEX BIT(10)
+
+#define PORT_REG_STATUS_SPEED_SHIFT 8
+#define PORT_REG_STATUS_SPEED_WIDTH 2
+#define PORT_REG_STATUS_SPEED_10 0
+#define PORT_REG_STATUS_SPEED_100 1
+#define PORT_REG_STATUS_SPEED_1000 2
+
+#define PORT_REG_STATUS_CMODE_MASK 0xF
+#define PORT_REG_STATUS_CMODE_100BASE_X 0x8
+#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
+#define PORT_REG_STATUS_CMODE_SGMII 0xa
+
+#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
+#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
+#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
+#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
+#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
+#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
+#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
+#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
+#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
+#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
+
+#define PORT_REG_CTRL_PSTATE_SHIFT 0
+#define PORT_REG_CTRL_PSTATE_WIDTH 2
+
+#define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
+#define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
+
+#define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
+#define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
+
+#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
+
+#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
+#define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
+
+/* Field values */
+#define PORT_REG_CTRL_PSTATE_DISABLED 0
+#define PORT_REG_CTRL_PSTATE_FORWARD 3
+
+#define PHY_REG_CTRL1_ENERGY_DET_OFF 0
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
+
+/* PHY Status Register */
+#define PHY_REG_STATUS1_SPEED 0xc000
+#define PHY_REG_STATUS1_GBIT 0x8000
+#define PHY_REG_STATUS1_100 0x4000
+#define PHY_REG_STATUS1_DUPLEX 0x2000
+#define PHY_REG_STATUS1_SPDDONE 0x0800
+#define PHY_REG_STATUS1_LINK 0x0400
+#define PHY_REG_STATUS1_ENERGY 0x0010