+ /* Wait for the bus to become free */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Set the data to write */
+ res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
+ SMI_DATA_REG, val);
+ if (res < 0)
+ return res;
+
+ /* Issue the write command */
+ res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+ smi_cmd_write(dev, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for the write command to complete */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ return 0;
+}
+
+static int mv88e61xx_phy_wait(struct phy_device *phydev)
+{
+ int val;
+ u32 timeout = 100;
+
+ do {
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD);
+ if (val >= 0 && (val & SMI_BUSY) == 0)
+ return 0;
+
+ mdelay(1);
+ } while (--timeout);
+
+ return -ETIMEDOUT;
+}
+
+static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
+ int devad, int reg)
+{
+ struct phy_device *phydev;
+ int res;
+
+ phydev = (struct phy_device *)smi_wrapper->priv;
+
+ /* Issue command to read */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD,
+ smi_cmd_read(dev, reg));
+
+ /* Wait for data to be read */
+ res = mv88e61xx_phy_wait(phydev);
+ if (res < 0)
+ return res;
+
+ /* Read retrieved data */
+ return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_DATA);
+}
+
+static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
+ int devad, int reg, u16 data)
+{
+ struct phy_device *phydev;
+ int res;
+
+ phydev = (struct phy_device *)smi_wrapper->priv;
+
+ /* Set the data to write */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_DATA, data);
+ if (res < 0)
+ return res;
+ /* Issue the write command */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD,
+ smi_cmd_write(dev, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for command to complete */
+ return mv88e61xx_phy_wait(phydev);
+}
+
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
+{
+ return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
+ MDIO_DEVAD_NONE, reg);
+}
+
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
+ int reg, u16 val)
+{
+ return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
+ MDIO_DEVAD_NONE, reg, val);
+}
+
+static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
+{
+ return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
+}
+
+static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
+ u16 val)
+{
+ return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
+}
+
+static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
+{
+ return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
+}
+
+static int mv88e61xx_get_switch_id(struct phy_device *phydev)
+{
+ int res;
+
+ res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
+ if (res < 0)
+ return res;
+ return res & 0xfff0;
+}
+
+static bool mv88e61xx_6352_family(struct phy_device *phydev)
+{
+ struct mv88e61xx_phy_priv *priv = phydev->priv;
+
+ switch (priv->id) {
+ case PORT_SWITCH_ID_6172:
+ case PORT_SWITCH_ID_6176:
+ case PORT_SWITCH_ID_6240:
+ case PORT_SWITCH_ID_6352:
+ return true;