+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ reg = phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR);
+
+ reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
+ reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
+ reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
+
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR, reg);
+ }
+
+ if (phy_interface_is_rgmii(phydev)) {
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
+ reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
+ else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ reg |= MIIM_88E151x_RGMII_RX_DELAY;
+ else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ reg |= MIIM_88E151x_RGMII_TX_DELAY;
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
+ }
+
+ /* soft reset */
+ phy_reset(phydev);
+
+ genphy_config_aneg(phydev);
+ genphy_restart_aneg(phydev);
+
+ return 0;
+}
+
+/* Marvell 88E1510 */
+static int m88e1510_config(struct phy_device *phydev)
+{
+ /* Select page 3 */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE,
+ MIIM_88E1118_PHY_LED_PAGE);
+
+ /* Enable INTn output on LED[2] */
+ m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL,
+ MIIM_88E151x_INT_EN_OFFS, 1, 1);
+
+ /* Configure LEDs */
+ /* LED[0]:0011 (ACT) */
+ m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
+ MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ,
+ MIIM_88E151x_LED0_ACT);
+ /* LED[1]:0110 (LINK 100/1000 Mbps) */
+ m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
+ MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ,
+ MIIM_88E151x_LED1_100_1000_LINK);
+
+ /* Reset page selection */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
+
+ return m88e1518_config(phydev);