- * Tested with Netgear GA622T (83820)
- * and SMC9452TX (83821)
- * NOTE: custom boards with these chips may (likely) require
- * a programmed EEPROM device (if present) in order to work
- * correctly.
+ * Tested with Netgear GA622T (83820)
+ * and SMC9452TX (83821)
+ * NOTE: custom boards with these chips may (likely) require
+ * a programmed EEPROM device (if present) in order to work
+ * correctly.
- TxDrthMask = 0x000000ff,
- TxFlthMask = 0x0000ff00,
+ TxDrthMask = 0x000000ff,
+ TxFlthMask = 0x0000ff00,
- TxMxdma_8 = 0x00100000,
- TxMxdma_16 = 0x00200000,
- TxMxdma_32 = 0x00300000,
- TxMxdma_64 = 0x00400000,
- TxMxdma_128 = 0x00500000,
- TxMxdma_256 = 0x00600000,
- TxMxdma_512 = 0x00700000,
- TxMxdma_1024 = 0x00000000,
- TxCollRetry = 0x00800000,
- TxAutoPad = 0x10000000,
- TxMacLoop = 0x20000000,
- TxHeartIgn = 0x40000000,
- TxCarrierIgn = 0x80000000
+ TxMxdma_8 = 0x00100000,
+ TxMxdma_16 = 0x00200000,
+ TxMxdma_32 = 0x00300000,
+ TxMxdma_64 = 0x00400000,
+ TxMxdma_128 = 0x00500000,
+ TxMxdma_256 = 0x00600000,
+ TxMxdma_512 = 0x00700000,
+ TxMxdma_1024 = 0x00000000,
+ TxCollRetry = 0x00800000,
+ TxAutoPad = 0x10000000,
+ TxMacLoop = 0x20000000,
+ TxHeartIgn = 0x40000000,
+ TxCarrierIgn = 0x80000000
- RxDrthMask = 0x0000003e,
- RxMxdmaMask = 0x00700000,
- RxMxdma_8 = 0x00100000,
- RxMxdma_16 = 0x00200000,
- RxMxdma_32 = 0x00300000,
- RxMxdma_64 = 0x00400000,
- RxMxdma_128 = 0x00500000,
- RxMxdma_256 = 0x00600000,
- RxMxdma_512 = 0x00700000,
- RxMxdma_1024 = 0x00000000,
- RxAcceptLenErr = 0x04000000,
- RxAcceptLong = 0x08000000,
- RxAcceptTx = 0x10000000,
- RxStripCRC = 0x20000000,
- RxAcceptRunt = 0x40000000,
- RxAcceptErr = 0x80000000,
+ RxDrthMask = 0x0000003e,
+ RxMxdmaMask = 0x00700000,
+ RxMxdma_8 = 0x00100000,
+ RxMxdma_16 = 0x00200000,
+ RxMxdma_32 = 0x00300000,
+ RxMxdma_64 = 0x00400000,
+ RxMxdma_128 = 0x00500000,
+ RxMxdma_256 = 0x00600000,
+ RxMxdma_512 = 0x00700000,
+ RxMxdma_1024 = 0x00000000,
+ RxAcceptLenErr = 0x04000000,
+ RxAcceptLong = 0x08000000,
+ RxAcceptTx = 0x10000000,
+ RxStripCRC = 0x20000000,
+ RxAcceptRunt = 0x40000000,
+ RxAcceptErr = 0x80000000,
- RxFilterEnable = 0x80000000,
- AcceptAllBroadcast = 0x40000000,
- AcceptAllMulticast = 0x20000000,
- AcceptAllUnicast = 0x10000000,
- AcceptPerfectMatch = 0x08000000,
+ RxFilterEnable = 0x80000000,
+ AcceptAllBroadcast = 0x40000000,
+ AcceptAllMulticast = 0x20000000,
+ AcceptAllUnicast = 0x10000000,
+ AcceptPerfectMatch = 0x08000000,
static void ns8382x_init_rxd(struct eth_device *dev);
static void ns8382x_set_rx_mode(struct eth_device *dev);
static void ns8382x_check_duplex(struct eth_device *dev);
static void ns8382x_init_rxd(struct eth_device *dev);
static void ns8382x_set_rx_mode(struct eth_device *dev);
static void ns8382x_check_duplex(struct eth_device *dev);
* Description: Retrieves the MAC address of the card, and sets up some
* globals required by other routines, and initializes the NIC, making it
* ready to send and receive packets.
* Description: Retrieves the MAC address of the card, and sets up some
* globals required by other routines, and initializes the NIC, making it
* ready to send and receive packets.
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
pci_write_config_dword(devno, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_write_config_dword(devno, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
sprintf(dev->name, "dp8382x#%d", card_number);
dev->iobase = bus_to_phys(iobase);
sprintf(dev->name, "dp8382x#%d", card_number);
dev->iobase = bus_to_phys(iobase);
rev = mdio_read(dev, phyAddress, PHYIDR2);
if ((rev & ~(0x000f)) == 0x00005c50 ||
(rev & ~(0x000f)) == 0x00005c60) {
rev = mdio_read(dev, phyAddress, PHYIDR2);
if ((rev & ~(0x000f)) == 0x00005c50 ||
(rev & ~(0x000f)) == 0x00005c60) {
-#ifdef NS8382X_DEBUG
- printf("phy rev is %x\n", rev);
- printf("phy address is %x\n",
+ debug("phy rev is %x\n", rev);
+ debug("phy address is %x\n",
dev->enetaddr[0], dev->enetaddr[1],
dev->enetaddr[2], dev->enetaddr[3],
dev->enetaddr[4], dev->enetaddr[5]);
}
dev->enetaddr[0], dev->enetaddr[1],
dev->enetaddr[2], dev->enetaddr[3],
dev->enetaddr[4], dev->enetaddr[5]);
}
* Description: resets the ethernet controller chip and configures
* registers and data structures required for sending and receiving packets.
* Arguments: struct eth_device *dev: NIC data structure
* Description: resets the ethernet controller chip and configures
* registers and data structures required for sending and receiving packets.
* Arguments: struct eth_device *dev: NIC data structure
tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
| TxCollRetry | TxMxdma_1024 | (0x1002);
rx_config = RxMxdma_1024 | 0x20;
tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
| TxCollRetry | TxMxdma_1024 | (0x1002);
rx_config = RxMxdma_1024 | 0x20;
-#ifdef NS8382X_DEBUG
- printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
- printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
-#endif
+
+ debug("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
+ debug("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
+
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
OUTL(dev, 0x0, TxRingPtrHi);
OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
OUTL(dev, 0x0, TxRingPtrHi);
OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
rxd[i].extsts = cpu_to_le32((u32) 0x0);
rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
rxd[i].extsts = cpu_to_le32((u32) 0x0);
rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
i, &rxd[i], le32_to_cpu(rxd[i].link),
le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
i, &rxd[i], le32_to_cpu(rxd[i].link),
le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
duplex = (config & FullDuplex) ? 1 : 0;
gig = (config & GigSpeed) ? 1 : 0;
hun = (config & HundSpeed) ? 1 : 0;
duplex = (config & FullDuplex) ? 1 : 0;
gig = (config & GigSpeed) ? 1 : 0;
hun = (config & HundSpeed) ? 1 : 0;
" capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
duplex ? "full" : "half");
" capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
duplex ? "full" : "half");
-#ifdef NS8382X_DEBUG
- printf("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
- printf("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
-#endif
+
+ debug("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
+ debug("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
+
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
OUTL(dev, config, ChipConfig);
}
/* Function: ns8382x_send
* Description: transmits a packet and waits for completion or timeout.
* Returns: void. */
OUTL(dev, config, ChipConfig);
}
/* Function: ns8382x_send
* Description: transmits a packet and waits for completion or timeout.
* Returns: void. */
{
u32 i, status = 0;
vu_long tx_stat = 0;
/* Stop the transmitter */
OUTL(dev, TxOff, ChipCmd);
{
u32 i, status = 0;
vu_long tx_stat = 0;
/* Stop the transmitter */
OUTL(dev, TxOff, ChipCmd);
/* load Transmit Descriptor Register */
OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
/* load Transmit Descriptor Register */
OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
/* restart the transmitter */
OUTL(dev, TxOn, ChipCmd);
for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
if (i >= TOUT_LOOP) {
/* restart the transmitter */
OUTL(dev, TxOn, ChipCmd);
for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
if (i >= TOUT_LOOP) {
/* Restore PME enable bit */
OUTL(dev, SavedClkRun, ClkRun);
}
/* Restore PME enable bit */
OUTL(dev, SavedClkRun, ClkRun);
}