+#ifdef CONFIG_DM_ETH
+static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
+{
+ fdt_addr_t addr;
+ void *gemgxl_regs;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ gemgxl_regs = (void __iomem *)addr;
+ if (!gemgxl_regs)
+ return -ENODEV;
+
+ /*
+ * SiFive GEMGXL TX clock operation mode:
+ *
+ * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
+ * and output clock on GMII output signal GTX_CLK
+ * 1 = MII mode. Use MII input signal TX_CLK in TX logic
+ */
+ writel(rate != 125000000, gemgxl_regs);
+ return 0;
+}
+
+int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
+{
+#ifdef CONFIG_CLK
+ struct macb_device *macb = dev_get_priv(dev);
+ struct clk tx_clk;
+ ulong rate;
+ int ret;
+
+ switch (speed) {
+ case _10BASET:
+ rate = 2500000; /* 2.5 MHz */
+ break;
+ case _100BASET:
+ rate = 25000000; /* 25 MHz */
+ break;
+ case _1000BASET:
+ rate = 125000000; /* 125 MHz */
+ break;
+ default:
+ /* does not change anything */
+ return 0;
+ }
+
+ if (macb->config->clk_init)
+ return macb->config->clk_init(dev, rate);
+
+ /*
+ * "tx_clk" is an optional clock source for MACB.
+ * Ignore if it does not exist in DT.
+ */
+ ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
+ if (ret)
+ return 0;
+
+ if (tx_clk.dev) {
+ ret = clk_set_rate(&tx_clk, rate);
+ if (ret)
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+#else