+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_RMII_MODE_SHIFT = 10,
+ RK3228_RMII_MODE_MASK = BIT(10),
+
+ RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3228_RMII_MODE_MASK |
+ RK3228_GMAC_PHY_INTF_SEL_MASK |
+ RK3228_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3228_TXCLK_DLY_ENA_GMAC_MASK,
+ RK3228_GMAC_PHY_INTF_SEL_RGMII |
+ DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
+
+ rk_clrsetreg(&grf->mac_con[0],
+ RK3228_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3228_CLK_TX_DL_CFG_GMAC_MASK,
+ pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
+static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3288_grf *grf;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->soc_con1,
+ RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
+ RK3288_GMAC_PHY_INTF_SEL_RGMII);
+
+ rk_clrsetreg(&grf->soc_con3,
+ RK3288_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3288_TXCLK_DLY_ENA_GMAC_MASK |
+ RK3288_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3288_CLK_TX_DL_CFG_GMAC_MASK,
+ DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
+ pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_SHIFT = 9,
+ RK3328_RMII_MODE_MASK = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3328_RMII_MODE_MASK |
+ RK3328_GMAC_PHY_INTF_SEL_MASK |
+ RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+ RK3328_GMAC_PHY_INTF_SEL_RGMII |
+ DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
+
+ rk_clrsetreg(&grf->mac_con[0],
+ RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3328_CLK_TX_DL_CFG_GMAC_MASK,
+ pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3368_grf *grf;
+ enum {
+ RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
+ RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
+ RK3368_RMII_MODE_MASK = BIT(6),
+ RK3368_RMII_MODE = BIT(6),
+ };
+ enum {
+ RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
+ RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
+ RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
+ RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
+ RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+ RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
+ RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+ RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->soc_con15,
+ RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
+ RK3368_GMAC_PHY_INTF_SEL_RGMII);
+
+ rk_clrsetreg(&grf->soc_con16,
+ RK3368_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3368_TXCLK_DLY_ENA_GMAC_MASK |
+ RK3368_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3368_CLK_TX_DL_CFG_GMAC_MASK,
+ DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
+ pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
+static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3399_grf_regs *grf;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ rk_clrsetreg(&grf->soc_con5,
+ RK3399_GMAC_PHY_INTF_SEL_MASK,
+ RK3399_GMAC_PHY_INTF_SEL_RGMII);
+
+ rk_clrsetreg(&grf->soc_con6,
+ RK3399_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3399_TXCLK_DLY_ENA_GMAC_MASK |
+ RK3399_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3399_CLK_TX_DL_CFG_GMAC_MASK,
+ DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
+ pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rv1108_grf *grf;
+
+ enum {
+ RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->gmac_con0,
+ RV1108_GMAC_PHY_INTF_SEL_MASK,
+ RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+