+
+ *final_reg_gsr = reg_gsr;
+ return 0;
+}
+
+int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
+{
+ int error = 0;
+ int portal_id = 0;
+ struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+ u64 mc_ram_addr = mc_get_dram_addr();
+ u32 reg_gsr;
+ u32 reg_mcfbalr;
+#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
+ const void *raw_image_addr;
+ size_t raw_image_size = 0;
+#endif
+ struct mc_version mc_ver_info;
+ u64 mc_ram_aligned_base_addr;
+ u8 mc_ram_num_256mb_blocks;
+ size_t mc_ram_size = mc_get_dram_block_size();
+
+
+ error = calculate_mc_private_ram_params(mc_ram_addr,
+ mc_ram_size,
+ &mc_ram_aligned_base_addr,
+ &mc_ram_num_256mb_blocks);
+ if (error != 0)
+ goto out;
+
+ /*
+ * Management Complex cores should be held at reset out of POR.
+ * U-boot should be the first software to touch MC. To be safe,
+ * we reset all cores again by setting GCR1 to 0. It doesn't do
+ * anything if they are held at reset. After we setup the firmware
+ * we kick off MC by deasserting the reset bit for core 0, and
+ * deasserting the reset bits for Command Portal Managers.
+ * The stop bits are not touched here. They are used to stop the
+ * cores when they are active. Setting stop bits doesn't stop the
+ * cores from fetching instructions when they are released from
+ * reset.
+ */
+ out_le32(&mc_ccsr_regs->reg_gcr1, 0);
+ dmb();
+
+#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
+ printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
+#else
+ error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr,
+ &raw_image_size);
+ if (error != 0)
+ goto out;
+ /*
+ * Load the MC FW at the beginning of the MC private DRAM block:
+ */
+ mc_copy_image("MC Firmware",
+ (u64)raw_image_addr, raw_image_size, mc_ram_addr);
+#endif
+ dump_ram_words("firmware", (void *)mc_ram_addr);
+
+ error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr);
+ if (error != 0)
+ goto out;
+
+ debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
+ dump_mc_ccsr_regs(mc_ccsr_regs);
+
+ /*
+ * Tell MC what is the address range of the DRAM block assigned to it:
+ */
+ reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
+ (mc_ram_num_256mb_blocks - 1);
+ out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
+ out_le32(&mc_ccsr_regs->reg_mcfbahr,
+ (u32)(mc_ram_aligned_base_addr >> 32));
+ out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
+
+ /*
+ * Tell the MC that we want delayed DPL deployment.
+ */
+ out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
+
+ printf("\nfsl-mc: Booting Management Complex ... ");
+
+ /*
+ * Deassert reset and release MC core 0 to run
+ */
+ out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
+ error = wait_for_mc(true, ®_gsr);
+ if (error != 0)
+ goto out;
+