-#define LAN91C96_MMU 0 // MMU Command Register
-#define LAN91C96_AUTO_TX_START 1 // Auto Tx Start Register
-#define LAN91C96_PNR 2 // Packet Number Register
-#define LAN91C96_ARR 3 // Allocation Result Register
-#define LAN91C96_FIFO 4 // FIFO Ports Register
-#define LAN91C96_POINTER 6 // Pointer Register
-#define LAN91C96_DATA_HIGH 8 // Data High Register
-#define LAN91C96_DATA_LOW 10 // Data Low Register
-#define LAN91C96_INT_STATS 12 // Interrupt Status Register - RO
-#define LAN91C96_INT_ACK 12 // Interrupt Acknowledge Register -WO
-#define LAN91C96_INT_MASK 13 // Interrupt Mask Register
+#define LAN91C96_MMU 0 /* MMU Command Register */
+#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */
+#define LAN91C96_PNR 2 /* Packet Number Register */
+#define LAN91C96_ARR 3 /* Allocation Result Register */
+#define LAN91C96_FIFO 4 /* FIFO Ports Register */
+#define LAN91C96_POINTER 6 /* Pointer Register */
+#define LAN91C96_DATA_HIGH 8 /* Data High Register */
+#define LAN91C96_DATA_LOW 10 /* Data Low Register */
+#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */
+#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */
+#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */