-
-#define RCAR_I2C_ICSCR 0x00
-#define RCAR_I2C_ICMCR 0x04
-#define RCAR_I2C_ICMCR_MDBS BIT(7)
-#define RCAR_I2C_ICMCR_FSCL BIT(6)
-#define RCAR_I2C_ICMCR_FSDA BIT(5)
-#define RCAR_I2C_ICMCR_OBPC BIT(4)
-#define RCAR_I2C_ICMCR_MIE BIT(3)
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+
+#define RCAR_I2C_ICSCR 0x00 /* slave ctrl */
+#define RCAR_I2C_ICMCR 0x04 /* master ctrl */
+#define RCAR_I2C_ICMCR_MDBS BIT(7) /* non-fifo mode switch */
+#define RCAR_I2C_ICMCR_FSCL BIT(6) /* override SCL pin */
+#define RCAR_I2C_ICMCR_FSDA BIT(5) /* override SDA pin */
+#define RCAR_I2C_ICMCR_OBPC BIT(4) /* override pins */
+#define RCAR_I2C_ICMCR_MIE BIT(3) /* master if enable */