- clrbits_le32(&gpio_regs->pupdr, (0x3 << i));
- setbits_le32(&gpio_regs->pupdr, ctl->pupd << i);
+#define CHECK_DSC(x) (!x || x->port > 6 || x->pin > 15)
+#define CHECK_CTL(x) (!x || x->mode > 3 || x->icnf > 3 || x->ocnf > 3 || \
+ x->pupd > 1)
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
+ const struct stm32_gpio_ctl *ctl)
+{
+ struct stm32_gpio_regs *gpio_regs;
+ u32 *cr;
+ int p, crp;
+ int rv;
+
+ if (CHECK_DSC(dsc)) {
+ rv = -EINVAL;
+ goto out;
+ }
+ if (CHECK_CTL(ctl)) {
+ rv = -EINVAL;
+ goto out;
+ }
+
+ p = dsc->pin;
+
+ gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
+
+ if (p < 8) {
+ cr = &gpio_regs->crl;
+ crp = p;
+ } else {
+ cr = &gpio_regs->crh;
+ crp = p - 8;
+ }
+
+ clrbits_le32(cr, 0x3 << STM32_GPIO_CR_MODE_SHIFT(crp));
+ setbits_le32(cr, ctl->mode << STM32_GPIO_CR_MODE_SHIFT(crp));
+
+ clrbits_le32(cr, 0x3 << STM32_GPIO_CR_CNF_SHIFT(crp));
+ /* Inputs set the optional pull up / pull down */
+ if (ctl->mode == STM32_GPIO_MODE_IN) {
+ setbits_le32(cr, ctl->icnf << STM32_GPIO_CR_CNF_SHIFT(crp));
+ clrbits_le32(&gpio_regs->odr, 0x1 << p);
+ setbits_le32(&gpio_regs->odr, ctl->pupd << p);
+ } else {
+ setbits_le32(cr, ctl->ocnf << STM32_GPIO_CR_CNF_SHIFT(crp));
+ }