+/* Simple SPL interface to GPIOs */
+#ifdef CONFIG_SPL_BUILD
+
+enum {
+ PULL_NONE_1V8 = 0,
+ PULL_DOWN_1V8 = 1,
+ PULL_UP_1V8 = 3,
+};
+
+int spl_gpio_set_pull(void *vregs, uint gpio, int pull)
+{
+ u32 *regs = vregs;
+ uint val;
+
+ regs += gpio >> GPIO_BANK_SHIFT;
+ gpio &= GPIO_OFFSET_MASK;
+ switch (pull) {
+ case GPIO_PULL_UP:
+ val = PULL_UP_1V8;
+ break;
+ case GPIO_PULL_DOWN:
+ val = PULL_DOWN_1V8;
+ break;
+ case GPIO_PULL_NORMAL:
+ default:
+ val = PULL_NONE_1V8;
+ break;
+ }
+ clrsetbits_le32(regs, 3 << (gpio * 2), val << (gpio * 2));
+
+ return 0;
+}
+
+int spl_gpio_output(void *vregs, uint gpio, int value)
+{
+ struct rockchip_gpio_regs * const regs = vregs;
+
+ clrsetbits_le32(®s->swport_dr, 1 << gpio, value << gpio);
+
+ /* Set direction */
+ clrsetbits_le32(®s->swport_ddr, 1 << gpio, 1 << gpio);
+
+ return 0;
+}
+#endif /* CONFIG_SPL_BUILD */
+