projects
/
oweals
/
u-boot.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
gpio: Add support for microblaze xilinx GPIO
[oweals/u-boot.git]
/
drivers
/
gpio
/
mxs_gpio.c
diff --git
a/drivers/gpio/mxs_gpio.c
b/drivers/gpio/mxs_gpio.c
index 539738be9b5a38df0085412aa2253f5f9f3630cc..29f19badda5ddf68c1bbe1c9bf11dc722adc3698 100644
(file)
--- a/
drivers/gpio/mxs_gpio.c
+++ b/
drivers/gpio/mxs_gpio.c
@@
-69,68
+69,64
@@
void mxs_gpio_init(void)
}
}
}
}
-int gpio_get_value(
int gp
)
+int gpio_get_value(
unsigned gpio
)
{
{
- uint32_t bank = PAD_BANK(gp);
+ uint32_t bank = PAD_BANK(gp
io
);
uint32_t offset = PINCTRL_DIN(bank);
uint32_t offset = PINCTRL_DIN(bank);
- struct mx
28_register
*reg =
- (struct mx
28_register
*)(MXS_PINCTRL_BASE + offset);
+ struct mx
s_register_32
*reg =
+ (struct mx
s_register_32
*)(MXS_PINCTRL_BASE + offset);
- return (readl(®->reg) >> PAD_PIN(gp)) & 1;
+ return (readl(®->reg) >> PAD_PIN(gp
io
)) & 1;
}
}
-void gpio_set_value(
int gp
, int value)
+void gpio_set_value(
unsigned gpio
, int value)
{
{
- uint32_t bank = PAD_BANK(gp);
+ uint32_t bank = PAD_BANK(gp
io
);
uint32_t offset = PINCTRL_DOUT(bank);
uint32_t offset = PINCTRL_DOUT(bank);
- struct mx
28_register
*reg =
- (struct mx
28_register
*)(MXS_PINCTRL_BASE + offset);
+ struct mx
s_register_32
*reg =
+ (struct mx
s_register_32
*)(MXS_PINCTRL_BASE + offset);
if (value)
if (value)
- writel(1 << PAD_PIN(gp), ®->reg_set);
+ writel(1 << PAD_PIN(gp
io
), ®->reg_set);
else
else
- writel(1 << PAD_PIN(gp), ®->reg_clr);
+ writel(1 << PAD_PIN(gp
io
), ®->reg_clr);
}
}
-int gpio_direction_input(
int gp
)
+int gpio_direction_input(
unsigned gpio
)
{
{
- uint32_t bank = PAD_BANK(gp);
+ uint32_t bank = PAD_BANK(gp
io
);
uint32_t offset = PINCTRL_DOE(bank);
uint32_t offset = PINCTRL_DOE(bank);
- struct mx
28_register
*reg =
- (struct mx
28_register
*)(MXS_PINCTRL_BASE + offset);
+ struct mx
s_register_32
*reg =
+ (struct mx
s_register_32
*)(MXS_PINCTRL_BASE + offset);
- writel(1 << PAD_PIN(gp), ®->reg_clr);
+ writel(1 << PAD_PIN(gp
io
), ®->reg_clr);
return 0;
}
return 0;
}
-int gpio_direction_output(
int gp
, int value)
+int gpio_direction_output(
unsigned gpio
, int value)
{
{
- uint32_t bank = PAD_BANK(gp);
+ uint32_t bank = PAD_BANK(gp
io
);
uint32_t offset = PINCTRL_DOE(bank);
uint32_t offset = PINCTRL_DOE(bank);
- struct mx
28_register
*reg =
- (struct mx
28_register
*)(MXS_PINCTRL_BASE + offset);
+ struct mx
s_register_32
*reg =
+ (struct mx
s_register_32
*)(MXS_PINCTRL_BASE + offset);
- writel(1 << PAD_PIN(gp), ®->reg_set);
+ writel(1 << PAD_PIN(gp
io
), ®->reg_set);
- gpio_set_value(gp, value);
+ gpio_set_value(gp
io
, value);
return 0;
}
return 0;
}
-int gpio_request(
int gp
, const char *label)
+int gpio_request(
unsigned gpio
, const char *label)
{
{
- if (PAD_BANK(gp) >= PINCTRL_BANKS)
- return -
EINVAL
;
+ if (PAD_BANK(gp
io
) >= PINCTRL_BANKS)
+ return -
1
;
return 0;
}
return 0;
}
-
void gpio_free(int gp
)
+
int gpio_free(unsigned gpio
)
{
{
-}
-
-void gpio_toggle_value(int gp)
-{
- gpio_set_value(gp, !gpio_get_value(gp));
+ return 0;
}
}