-static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
-{
- u32 gpio_offset[2];
- int pad_offset;
- int val;
- int ret;
- const void *prop;
-
- /*
- * GPIO node is not mandatory, so we only do the
- * pinmuxing if the node exist.
- */
- ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
- gpio_offset, 2);
- if (!ret) {
- /* Do we want to force the GPIO mode? */
- prop = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio",
- NULL);
- if (prop)
- _ich6_gpio_set_function(GPIO_USESEL_OFFSET
- (gpiobase) +
- gpio_offset[0],
- gpio_offset[1], 1);
-
- val =
- fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
- if (val != -1)
- _ich6_gpio_set_direction(GPIO_IOSEL_OFFSET
- (gpiobase) +
- gpio_offset[0],
- gpio_offset[1], val);
-
- val =
- fdtdec_get_int(gd->fdt_blob, pin_node, "output-value", -1);
- if (val != -1)
- _ich6_gpio_set_value(GPIO_LVL_OFFSET(gpiobase)
- + gpio_offset[0],
- gpio_offset[1], val);
- }
-
- /* if iobase is present, let's configure the pad */
- if (iobase != -1) {
- int iobase_addr;
-
- /*
- * The offset for the same pin for the IOBASE and GPIOBASE are
- * different, so instead of maintaining a lookup table,
- * the device tree should provide directly the correct
- * value for both mapping.
- */
- pad_offset =
- fdtdec_get_int(gd->fdt_blob, pin_node, "pad-offset", -1);
- if (pad_offset == -1) {
- debug("%s: Invalid register io offset %d\n",
- __func__, pad_offset);
- return -EINVAL;
- }
-
- /* compute the absolute pad address */
- iobase_addr = iobase + pad_offset;
-
- /*
- * Do we need to set a specific function mode?
- * If someone put also 'mode-gpio', this option will
- * be just ignored by the controller
- */
- val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
- if (val != -1)
- clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
-
- /* Configure the pull-up/down if needed */
- val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
- if (val != -1)
- clrsetbits_le32(iobase_addr,
- IOPAD_PULL_ASSIGN_MASK,
- val << IOPAD_PULL_ASSIGN_SHIFT);
-
- val =
- fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength", -1);
- if (val != -1)
- clrsetbits_le32(iobase_addr,
- IOPAD_PULL_STRENGTH_MASK,
- val << IOPAD_PULL_STRENGTH_SHIFT);
-
- debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
- readl(iobase_addr));
- }
-
- return 0;
-}
-
-int gpio_ich6_pinctrl_init(void)
-{
- int pin_node;
- int node;
- int ret;
- int gpiobase;
- int iobase_offset;
- int iobase = -1;
-
- /*
- * Get the memory/io base address to configure every pins.
- * IOBASE is used to configure the mode/pads
- * GPIOBASE is used to configure the direction and default value
- */
- gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE);
- if (gpiobase < 0) {
- debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
- gpiobase);
- return -EINVAL;
- }
-
- /* This is not an error to not have a pinctrl node */
- node =
- fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_X86_PINCTRL);
- if (node <= 0) {
- debug("%s: no pinctrl node\n", __func__);
- return 0;
- }
-
- /*
- * Get the IOBASE, this is not mandatory as this is not
- * supported by all the CPU
- */
- iobase_offset = fdtdec_get_int(gd->fdt_blob, node, "io-base", -1);
- if (iobase_offset == -1) {
- debug("%s: io-base offset not present\n", __func__);
- } else {
- iobase = gpio_ich6_get_base(iobase_offset);
- if (IS_ERR_VALUE(iobase)) {
- debug("%s: invalid IOBASE address (%08x)\n", __func__,
- iobase);
- return -EINVAL;
- }
- }
-
- for (pin_node = fdt_first_subnode(gd->fdt_blob, node);
- pin_node > 0;
- pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
- /* Configure the pin */
- ret = _gpio_ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
- if (ret != 0) {
- debug("%s: invalid configuration for the pin %d\n",
- __func__, pin_node);
- return ret;
- }
- }
-
- return 0;
-}
-