/* Choose ddr controller address mirror mode */
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
/* Choose ddr controller address mirror mode */
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
* Set this to 0 for global auto precharge
* The value of 0x100 has been used for DDR1, DDR2, DDR3.
* It is not wrong. Any value should be OK. The performance depends on
* Set this to 0 for global auto precharge
* The value of 0x100 has been used for DDR1, DDR2, DDR3.
* It is not wrong. Any value should be OK. The performance depends on
- popts->bstopre = 0x100;
-
- /* Minimum CKE pulse width -- tCKE(MIN) */
- popts->tcke_clock_pulse_width_ps
- = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
+ popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
+ >> 2;
* FIXME: width, was considering looking at pdimm->primary_sdram_width
*/
#if defined(CONFIG_SYS_FSL_DDR1)
* FIXME: width, was considering looking at pdimm->primary_sdram_width
*/
#if defined(CONFIG_SYS_FSL_DDR1)